A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-Al.sub.yGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al.sub.yGaN buffer layer, and an i-Al.sub.xGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 Ω.Math.cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 μm, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm.sup.3 and a specific resistance of 100 to 1000 Ω.Math.cm.

The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 Ω.Math.cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 μm, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm.sup.3 and a specific resistance of 100 to 1000 Ω.Math.cm.

According to one embodiment, a semiconductor device includes a substrate, and a first semiconductor layer including magnesium and Al.sub.x1Ga.sub.1−x1N. The first semiconductor layer includes first, second, and third regions. The first region is between the substrate and the third region. The second region is between the first and third regions. A first concentration of magnesium in the first region is greater than a third concentration of magnesium in the third region. A second concentration of magnesium in the second region decreases along a first orientation. The first orientation is from the substrate toward the first semiconductor layer. A second change rate of a logarithm of the second concentration with respect to a change of a position along the first orientation is greater than a third change rate of a logarithm of the third concentration with respect to the change of the position along the first orientation.

According to one embodiment, a semiconductor device includes a substrate, and a first semiconductor layer including magnesium and Al.sub.x1Ga.sub.1−x1N. The first semiconductor layer includes first, second, and third regions. The first region is between the substrate and the third region. The second region is between the first and third regions. A first concentration of magnesium in the first region is greater than a third concentration of magnesium in the third region. A second concentration of magnesium in the second region decreases along a first orientation. The first orientation is from the substrate toward the first semiconductor layer. A second change rate of a logarithm of the second concentration with respect to a change of a position along the first orientation is greater than a third change rate of a logarithm of the third concentration with respect to the change of the position along the first orientation.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.