Patent classifications
H01L29/2206
Semiconductor device with a fin-shaped active region and a gate electrode
A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
Thin Film Transistor Array Substrate for Digital X-Ray Detector Device, Digital X-Ray Detector Device, and Manufacturing Method Thereof
The present disclosure relates to a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device and a manufacturing method thereof. The thin film transistor array substrate comprises: a base substrate comprising a driving area and a non-driving area; at least one PIN diode disposed within the driving area of the base substrate and comprising a lower electrode, a PIN layer, and an upper electrode; and at least one align mark disposed within the non-driving area of the base substrate, wherein the align mark comprises a first align mark layer, an align PIN layer, and a second align mark layer.
Self-aligned top-gated non-planar oxide semiconductor thin film transistors
Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.
Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element
A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.
Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element
A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.
Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element
A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.
COMPOSITE OXIDE SEMICONDUCTOR AND TRANSISTOR
A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.
Thin film transistors with a crystalline oxide semiconductor source/drain
Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.
Semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes
Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).
Composite oxide semiconductor and transistor
A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.