A semiconductor device which includes a metal oxide film including a crystal part is provided. A semiconductor device which has a metal oxide film and high field-effect mobility is provided. A highly reliable semiconductor device including a metal oxide film is provided. The semiconductor device includes a first insulator, a first conductor formed over the first insulator, a second insulator formed over the first conductor, an oxide formed over the second insulator, a third insulator formed over the oxide, a second conductor formed over the third insulator, a fourth insulator formed over the third insulator and the second conductor, and a fifth insulator formed over the fourth insulator. The oxide contains In, M (M is Al, Ga, Y, or Sn), and Zn. The oxide includes a first crystal part and a second crystal part. The first crystal part has c-axis alignment. The second crystal part does not have c-axis alignment.

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.

Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

The TFT includes a substrate, a gate electrode, a gate insulation layer, an active layer, a source electrode, and a drain electrode. The gate electrode has a first lateral surface and a second lateral surface opposite to each other. The gate electrode is disposed on the substrate. The gate insulation layer covers the gate electrode. The active layer is disposed on the gate insulation layer, and has a first lateral surface and a second lateral surface opposite to each other. The source electrode is disposed adjacent to the first lateral surface of the active layer. The source electrode and the first lateral surface of the gate electrode are co-planar or have a first lateral gap. The drain electrode is disposed adjacent to the second lateral surface of the active layer. The drain electrode and the second lateral surface of the gate electrode are co-planar or have a second lateral gap.

A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide.

Provided is a semiconductor device (100A) including: a substrate (1); a first gate electrode (2) that is provided on the substrate; a first gate insulating layer (3) that covers the first gate electrode; a first oxide semiconductor layer (4) that faces the first gate electrode with the first gate insulating layer in between; a first source electrode (5) and a first drain electrode (6) that are electrically connected to the first oxide semiconductor layer; a second gate insulating layer (7) that covers the first oxide semiconductor layer; a second gate electrode (8) that faces the first oxide semiconductor layer with the second gate insulating layer in between; a third gate insulating layer (9) that covers the second gate electrode; a second oxide semiconductor layer (10) that faces the second gate electrode with the third gate insulating layer in between; and a second source electrode (11) and a second drain electrode (12) that are electrically connected to the second oxide semiconductor layer.

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

A laminate contains a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer comprising a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide, wherein the crystal region is an epitaxially grown layer from a crystal plane of the crystal substrate.

The film structure according to an embodiment of the present invention includes at least one active monolayer having an energy level quantized in at least one axial direction and at least one barrier alternately stacked with the at least one active monolayer. Current flows through the active monolayer, and the current flow may be limited by the quantized energy level.