A HEMT made of nitride semiconductor materials and a process of forming the same are disclosed, where the HEMT has n-type regions beneath the source and drain electrodes with remarkably increased carrier concentration. The HEMT provides the n-type regions made of at least one of epitaxially grown ZnO layer and MgZnO layer each doped with at least aluminum and gallium with density higher than 110.sup.20 cm.sup.3. The process of forming the HEMT includes steps of forming recesses by dry-etching, epitaxially growing n-type layer, removing surplus n-type layer except within the recesses by dry-etching using hydrocarbon, and forming the electrodes on the n-type layer.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

The present invention relates to a method for manufacturing a transistor according selective printing of a dopant. For the manufacture of a transistor, a semiconductor layer is formed on a substrate, and a dopant layer is formed on the semiconductor layer. In the formation of the dopant layer, an inkjet printing is used to selectively print an n type dopant or a p type dopant.

A light diffusion member includes a matrix and a number of quantum dots uniformly dispersed in the matrix. The matrix is made of epoxy resin and ammonium persulfate. The quantum dots have a mass percentage of about 10% to about 20% of the total mass of the light diffusion member. A light emitting device using the light diffusion member and a display device using the light emitting device are also provided.

A carbon allotrope and a display device including the same are disclosed. The thin-film transistor array substrate, comprising a substrate, a gate electrode on the substrate, an active layer comprising a first active layer, which opposes the gate electrode and is adjacent to the gate electrode thereby comprising a semiconductor material and a plurality of carbon allotropes, and a second active layer, which is in contact with the first active layer and comprises a semiconductor material, a gate insulating film between the gate electrode and the active layer, and a source electrode and a drain electrode respectively in contact with the active layer.

A carbon allotrope and a display device including the same are disclosed. The thin-film transistor array substrate, comprising a substrate, a gate electrode on the substrate, an active layer comprising a first active layer, which opposes the gate electrode and is adjacent to the gate electrode thereby comprising a semiconductor material and a plurality of carbon allotropes, and a second active layer, which is in contact with the first active layer and comprises a semiconductor material, a gate insulating film between the gate electrode and the active layer, and a source electrode and a drain electrode respectively in contact with the active layer.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8 cm.sup.2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

The invention generally relates to methods of thermal doping by vacancy formation in nanocrystals, devices and uses thereof.