Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

The present invention provides processes for preparing metal oxide semiconductor nanomaterials.

A two-dimensional electronic component includes a substrate; an artificial two-dimensional (2D) material disposed on the substrate; and a first metallic electrode disposed on the artificial 2D material. The artificial 2D material includes a layered atomic structure including a middle atomic layer, a lower atomic layer disposed on a lower surface of the middle atomic layer, and an upper atomic layer disposed on an upper surface of the middle atomic layer respectively. The upper atomic layer and the first metallic electrode are attracted together at a junction therebetween by metallic bonding.

A method for atomically manipulating an artificial two-dimensional material includes providing a first artificial two-dimensional (2D) material having a layered atomic structure; placing the first artificial 2D material in a vacuumed reactive chamber; using plasma to remove an atomic layer on one surface of the first artificial 2D material to expose unsaturated compounds; introducing heterogeneous atoms into the vacuumed reactive chamber, the heterogeneous atoms being different from atoms on the other surface of the first artificial 2D material; and binding the heterogeneous atoms with the unsaturated compounds to form a second artificial 2D material having two heterogeneous junctions.

Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

The present disclosure provides a semiconductor heterojunction. The semiconductor heterojunction includes a bottom semiconductor, a top semiconductor and an electrode substrate. An upper surface of the bottom semiconductor includes a first facet. A lower surface of the top semiconductor includes a second facet, and the lower surface of the top semiconductor is contacted with the upper surface of the bottom semiconductor. The electrode substrate is disposed below the bottom semiconductor.

An object is to provide a technology for enabling prevention of deterioration of characteristics of an oxide semiconductor device. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, a p-type oxide semiconductor layer, and an oxide layer. The p-type oxide semiconductor layer is disposed above the n-type gallium oxide epitaxial layer, contains an element different from gallium as a main component, and has p-type conductivity. The oxide layer is disposed between the n-type gallium oxide epitaxial layer and the p-type oxide semiconductor layer, and is made of a material different from gallium oxide and different at least partly from a material of the p-type oxide semiconductor layer.

Embodiments of this disclosure include apparatus, systems, and methods for fabricating monolayers. In one example, a method includes forming a multilayer film having a plurality of monolayers of a two-dimensional (2D) material on a growth substrate. The multilayer film has a first side proximate the growth substrate and a second side opposite the first side.

In one aspect, composite materials including a thin-film layer of lateral p-n junctions are described herein, which can be employed in circuits or various components of electrical devices. Briefly, a composite material comprises a thin-film layer including p-type regions alternating with n-type regions along a face of the thin-film layer, the p-type regions comprising electrically conductive particles dispersed in a first organic carrier and the n-type regions comprising electrically conductive particles dispersed in a second organic carrier, wherein p-n junctions are established at interfaces between the p-type and n-type regions. As described further herein, the thin-film layer is flexible, permitting the thin-film to be folded or arranged into a number of configurations to provide various circuits or components of electrical devices.

An object is to provide a technology for enabling prevention of deterioration of characteristics of an oxide semiconductor device. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, a p-type oxide semiconductor layer, and an oxide layer. The p-type oxide semiconductor layer is disposed above the n-type gallium oxide epitaxial layer, contains an element different from gallium as a main component, and has p-type conductivity. The oxide layer is disposed between the n-type gallium oxide epitaxial layer and the p-type oxide semiconductor layer, and is made of a material different from gallium oxide and different at least partly from a material of the p-type oxide semiconductor layer.