A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

An n-type semiconductor layer has a single-crystal structure and is made of a wide-gap semiconducting material. A p-type semiconductor layer is provided on the n-type semiconductor layer and made of a material different from the aforementioned wide-gap semiconducting material, and has either a microcrystalline structure or an amorphous structure. An electrode is provided on at least one of the n-type semiconductor layer and the p-type semiconductor layer.

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

The first object of the invention is directed to field-effect gate transistor comprising (a) a substrate, (b) a source terminal, (c) a drain terminal, and (d) a channel between the source terminal and the drain terminal, the channel being a layer of Cu.sub.xCr.sub.yO.sub.2 in which the y/x ratio is superior to 1. The field-effect gate transistor is remarkable in that the channel of Cu.sub.xCr.sub.yO.sub.2 presents a gradient of holes concentration. The second object of the invention is directed to a method for laser annealing a field-effect gate transistor in accordance with the first object of the invention.

The present invention provides processes for preparing metal oxide semiconductor nanomaterials.

An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

A semiconductor layer of the present invention is a semiconductor layer including: a pn junction at which an n-type semiconductor (Al.sub.2O.sub.3 (n-type)) and a p-type semiconductor (Al.sub.2O.sub.3 (p-type)) are joined, the n-type semiconductor (Al.sub.2O.sub.3 (n-type)) having a donor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain aluminum (Al), the p-type semiconductor (Al.sub.2O.sub.3 (p-type)) having an acceptor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain oxygen (O).

Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

A high output and high speed electronic device having low cost and high productivity is disclosed. The copper halide semiconductor based electronic device, includes a substrate, a copper halide channel layer formed on the substrate, an insulating layer formed on the copper halide channel layer, a gate electrode formed on the insulating layer, a first n+copper halide layer formed on the copper halide channel layer to be disposed at a first side of the gate electrode, the first n+copper halide layer comprising n-type impurities, a drain electrode formed on the first n+copper halide layer, a second n+copper halide layer formed on the copper halide channel layer to be disposed at a second side of the gate electrode, which is opposite to the first side, the second n+copper halide layer comprising n-type impurities, and a source electrode formed on the second n+copper halide layer.

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.