A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoO.sub.xN.sub.y, where each of “x” and “y” is from 0 to 4.0; and (b): MoM.sub.z, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.

A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes gate electrode layers and interlayer insulation structures that are alternately stacked with each other. The semiconductor device includes a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. Each of the interlayer insulation structure includes an insulation layer and a metal-organic framework layer that are disposed on the same plane.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a first channel structure and a second channel structure, extending in a first direction; a third channel structure disposed between the first channel structure and the second channel structure, the third channel structure extending in the first direction; and a plurality of conductive layers surrounding the first channel structure, the second channel structure, and the third channel structure, the plurality of conductive layers being stacked to be spaced apart from each other in the first direction. The third channel structure is spaced apart from the first channel structure and the second channel structure without interposition of the plurality of conductive layers.

A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar extends through the stack structure. The at least one pillar includes at least one insulative material and a channel structure horizontally surrounding the at least one insulative material. The at least one channel structure comprises sub-regions of semiconductor material. At least one of the sub-regions exhibits a different microstructure than at least one other of the sub-regions. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.