A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

Provided is a technique for preventing a peak current during recovery while enhancing breakdown voltage. A semiconductor device includes the following: a p.sup.-type anode layer having a uniform p-type impurity concentration; an n.sup.-type layer having a distributed n-type impurity concentration; and an n.sup.+-type layer disposed with the n.sup.-type layer interposed between the n.sup.+-type layer and the p.sup.-type anode layer, the n.sup.+-type layer having an n-type impurity concentration that is higher than that of the n.sup.-type layer and is uniform. The n-type impurity concentration of the n.sup.-type layer in a portion on the p.sup.-type-anode-layer side is lower than the p-type impurity concentration of the p.sup.-type anode layer.

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

A silicon controlled rectifier includes a P-type substrate, an N-type doped well, a first P-type strip-shaped heavily-doped area arranged in the N-type doped well, a first N-type strip-shaped heavily-doped area arranged in the P-type substrate, and at least one N-type heavily-doped area arranged in the P-type substrate and the N-type doped well. The at least one N-type heavily-doped area is not arranged between the first P-type strip-shaped heavily-doped area and the first N-type strip-shaped heavily-doped area, thus the surface area of a semiconductor substrate can be reduced. The conductivity types of the abovementioned components are alternatively changed.

A silicon controlled rectifier includes a P-type substrate, an N-type doped well, a first P-type strip-shaped heavily-doped area arranged in the N-type doped well, a first N-type strip-shaped heavily-doped area arranged in the P-type substrate, and at least one N-type heavily-doped area arranged in the P-type substrate and the N-type doped well. The at least one N-type heavily-doped area is not arranged between the first P-type strip-shaped heavily-doped area and the first N-type strip-shaped heavily-doped area, thus the surface area of a semiconductor substrate can be reduced. The conductivity types of the abovementioned components are alternatively changed.