A power diode comprises a plurality of diode cells (10). Each diode cell (10) comprises a first conductivity type first anode layer (40), a first conductivity type second anode layer (45) having a lower doping concentration than the first anode layer (40) and being separated from an anode electrode layer (20) by the first anode layer (40), a second conductivity type drift layer (50) forming a pn-junction with the second anode layer (45), a second conductivity type cathode layer (60) being in direct contact with the cathode electrode layer (60), and a cathode-side segmentation layer (67) being in direct contact with the cathode electrode layer (30). A material of the cathode-side segmentation layer (67) is a first conductivity type semiconductor, wherein an integrated doping content of the cathode-side, which is integrated along a direction perpendicular to the second main side (102), is below 2.Math.10.sup.13 cm.sup.−2, or a material of the cathode-side segmentation layer (67) is an insulating material. A horizontal cross-section through each diode cell (10) along a horizontal plane (K1) comprises a first area where the horizontal plane (K1) intersects the second anode layer (45) and a second area where the plane (K1) intersects the drift layer (50).

A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second conduction type complementary to the first conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode with a rear-side electrode width, and the front-side base region is electrically connected to a front-side electrode with a front-side electrode width. A turn-on structure with a turn-on structure width is embedded into the front-side and/or rear-side base region and is covered by the respective electrode. The turn-on structure is configured to be turned on depending on a supplied turn-on signal and to produce, on a one-off basis, an irreversible, low-resistance connection between the two electrodes. The ratio of the turn-on structure width to the respective electrode width is less than 1.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n− drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

A module (100) is specified, the module (100) comprising a first module connection (108), a second module connection (109), an energy store (105), a first electrical switch (101) and a second electrical switch (102), wherein a switchable bypass device (1) is arranged between the first module connection (108) and the second module connection (109) and wherein the switchable bypass device (1) is configured to remain in a bidirectional current conducting state in response to a single trigger pulse.

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Disclosed herein are gated thyristors and related devices and techniques. In some embodiments, an integrated circuit (IC) device may include a metal portion and a gated thyristor on the metal portion. The gated thyristor may include a stack of alternating p-type and n-type material layers, and the stack may be on the metal portion. The IC device may further include a gate line spaced apart from one of the material layers by a gate dielectric.

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.