A transistor structure, includes a buffer layer and a quantum well channel layer on top of the buffer layer. There is a barrier layer on top of the channel layer. There is a drain contact on a channel stack. A source contact is on a channel stack. A gate structure is located between the source contact and drain contact, comprising: an active gate portion having a bottom surface in contact with a bottom surface of the source and the drain contacts. A superconducting portion of the gate structure is in contact with, and adjacent to, an upper part of the active gate portion.

Systems and methods are provided that enable the production of semiconductor devices having a metal nitride layer in direct contact with a semiconductor layer to form a Schottky diode, such as a TiN gate on an AlGaN/GaN high electron mobility transistor (HEMT). Metal nitrides offer exceptional thermal stability and a lower diffusion coefficient. Technology enabled by embodiments of the present disclosure improves the reliability of GaN-based microwave power transistors.

High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, gate-connected field plate, and source-connected field plate.

The present invention discloses a method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz: sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulated N-polar GaN layer, a non-doped N-polar AlGaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a rectifier epitaxial wafer; preparing a pattern groove for a schottky contact electrode on the GaN rectifier epitaxial wafer, and depositing the schottky contact electrode in the groove; preparing a pattern for an ohmic contact electrode, and depositing a device ohmic contact electrode on the surface of the epitaxial wafer; subsequently, depositing a silicon nitride passivation layer at a part where there is no electrode on the surface of the epitaxial wafer, and preparing a surface electrode area; and finally, performing mesa isolation treatment on the GaN rectifier epitaxial wafer. The present invention realizes the preparation of a high-frequency GaN rectifier, and improves the performance stability of a rectifier device operating at a high power.

A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.

A semiconductor device includes a substrate, a back-barrier layer arranged on the substrate, the back-barrier layer including first p-type dopant atoms, an intermediate or nucleation layer having a lattice constant different from a lattice constant of the back-barrier layer, a semiconductor heterostructure having a channel layer, a spacer layer on the channel layer and a barrier layer on the spacer layer, wherein a combination of materials of the barrier layer, the spacer layer and the channel layer is selected such that a carrier charge is provided to the channel layer, a gate layer arranged to partially cover a top of the barrier layer, wherein the gate layer includes second p-type dopant atoms, and a set of electrodes for providing and controlling the carrier charge in the carrier channel.

A semiconductor apparatus having a trench Schottky barrier Schottky diode, which includes: a semiconductor volume of a first conductivity type, which semiconductor volume has a first side covered with a metal layer, and at least one trench extending in the first side and at least partly filled with metal. At least one wall segment of the trench, and/or at least one region, located next to the trench, of the first side covered with the metal layer, is separated by a layer, located between the metal layer and the semiconductor volume, made of a first semiconductor material of a second conductivity type.

We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.

A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an N surface of a nitride semiconductor substrate. The process of forming the metal layer includes a first process of forming a metal layer by sputtering at a film formation rate controlled to 4 nm/minute or lower.

A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.