HIGH VOLTAGE SEMICONDUCTOR DEVICES

Abstract

We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.

Claims

1. A high voltage semiconductor device comprising: a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on a surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from the surface of the device.

2. A device according to claim 1, further comprising a first semiconductor region of the second conductivity type located between the semiconductor substrate and the semiconductor drift region.

3. A device according to claim 1 or 2, wherein the semiconductor region within the drift region is a second semiconductor region.

4. A device according to any preceding claim, wherein the lateral extension is vertically spaced from the surface of the device.

5. A device according to any preceding claim, wherein the entire lateral extension is vertically spaced from the surface of the device.

6. A device according to claim 3, 4 or 5, wherein the lateral extension extends laterally only from a deeper portion of the second semiconductor region.

7. A device according to any of claims 3 to 6, wherein the doping concentration of the lateral extension is lower than the second semiconductor region.

8. A device according to any preceding claim, further comprising a first ohmic contact operatively connected to the substrate and a second ohmic contact formed on the second semiconductor region.

9. A device according to claim 8, further comprising a field plate extending from the second ohmic contact over the drift region.

10. A device according to claim 9, wherein the lateral extension extends towards the field plate into the drift region.

11. A device according to any preceding claim, wherein the device is a vertical PIN diode.

12. A device according to any preceding claim, further comprising at least one floating guard ring of the first conductivity type laterally spaced from the highly doped semiconductor region of the first conductivity type within the drift region.

13. A device according to claim 12, further comprising a lateral extension of the first conductivity type extending laterally from the at least one guard ring into the drift region.

14. A device according to claim 11, 12 or 13, wherein the device is a termination structure.

15. A device according to any one of claims 1 to 8, further comprising a Schottky metal contact formed directly on the semiconductor drift region on the surface of the device.

16. A device according to claim 15, wherein the lateral extension extends laterally towards the Schottky metal contact.

17. A device according to any of claims 2 to 16, wherein the semiconductor substrate, the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise monocrystalline silicon material.

18. A device according to any of claims 2 to 16, wherein the semiconductor substrate, the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise 4H-SiC.

19. A device according to any of claims 2 to 16, wherein the semiconductor substrate comprises monocrystalline silicon material, and the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise 3C-SiC.

20. A device according to any of claims 2 to 16, wherein the semiconductor substrate, the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise GaN.

21. A device according to any of claims 2 to 16, wherein the semiconductor substrate comprises monocrystalline silicon material, and the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise GaN.

22. A device according to any of claims 2 to 16, wherein the semiconductor substrate comprises SiC material, and the first semiconductor region, the drift region, the second semiconductor region and the lateral extension each comprise GaN.

23. A wide band-gap high voltage semiconductor transistor comprising: a semiconductor substrate; a semiconductor drift region of a second conductivity type disposed on the semiconductor substrate; a body region of a first conductivity type, opposite the second conductivity type, located within the semiconductor drift region; a source region of the second conductivity type located within the body region; a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; wherein the body region comprises a lateral extension of the first conductivity type extending laterally into the drift region, the lateral extension being spaced from the surface of the transistor.

24. A transistor according to claim 23, wherein the surface of the transistor is parallel to the channel region.

25. A transistor according to claim 23 or 24, wherein the lateral extension is vertically spaced from the surface of the transistor.

26. A transistor according to claim 23, 24 or 25, wherein the body region comprises a first portion adjacent the gate and a second portion located deeper than the first portion, the doping concentration of the first portion being higher than the doping concentration of the second portion.

27. A transistor according to claim 26, wherein the lateral extension extends laterally only from the second deeper portion of the body region.

28. A transistor according to claim 26 or 27, wherein the doping concentration of the lateral extension is substantially the same as the doping concentration of the second deeper portion of the body region.

29. A transistor according to any one of claims 23 to 28, wherein the lateral extension extends from the body region in a lateral direction which is opposite to a direction to which the gate extends from the source to the drift region.

30. A transistor according to claim 29, wherein the transistor forms adjacent to a termination structure of the transistor.

31. A transistor according to claim 29 or 30, further comprising a field insulator adjacent the source region and a source electrode extending over the field insulator, wherein the lateral extension extends further into the drift region compared to the field plate extending over the field insulator.

32. A transistor according to claim 31, wherein the thickness of the field insulator, the doping concentration of the lateral extension and the field plate extension over the field insulator are adjusted together so that an improved breakdown voltage is achieved.

33. A transistor according to any one of claims 23 to 28, wherein the lateral extension extends from the body region in a lateral direction which is in the same direction to which the gate extends from the source to the drift region.

34. A transistor according to any one of claims 23 to 33, wherein the transistor is configured such that the electric field formed at vertical junctions between the lateral extension and the drift region reduces an electric field formed between the body region and drift region at the surface of the transistor.

35. A transistor according to any one of claims 23 to 34, wherein the semiconductor substrate comprises monocrystalline silicon material.

36. A transistor according to claim 35, wherein the semiconductor drift region, the body region, the lateral extension and the source region each comprise a material comprising 3-step cubic silicon carbide (3C-SiC).

37. A transistor according to any one of claims 23 to 34, wherein the semiconductor substrate, the semiconductor drift region, the body region, the lateral extension and the source region each comprise a material comprising 4H-SiC.

38. A transistor according to any one of claims 23 to 34, wherein the semiconductor substrate, the semiconductor drift region, the body region, the lateral extension and the source region each comprise a material comprising GaN.

39. A transistor according to any one of claims 23 to 34, wherein the semiconductor substrate comprises monocrystalline silicon material, and the semiconductor drift region, the body region, the lateral extension and the source region each comprise a material comprising GaN.

40. A transistor according to any one of claims 23 to 34, wherein the semiconductor substrate comprises SiC material, and the semiconductor drift region, the body region, the lateral extension and the source region each comprise a material comprising GaN.

41. A transistor according to any one of claims 23 to 40, further comprising a first semiconductor region disposed between the semiconductor substrate and the drift region, the first semiconductor region comprising a material comprising 3C-SiC, 4H-SiC or GaN.

42. A transistor according to claim 41, wherein the first semiconductor region is of the second conductivity type and the semiconductor substrate is of the second conductivity type.

43. A transistor according to claim 42, wherein the transistor is a vertical power metal-oxide-semiconductor field effect transistor (MOSFET).

44. A transistor according to claim 41, wherein the first semiconductor region is of the first conductivity type and the semiconductor substrate is of the first conductivity type.

45. A transistor according to claim 44, wherein the transistor is a vertical power insulated gate bipolar transistor (IGBT).

46. A method of manufacturing a high voltage semiconductor device, the method comprising: forming a semiconductor substrate of a second conductivity type; forming a semiconductor drift region of the second conductivity type disposed over the semiconductor drift region, the semiconductor substrate having higher doping concentration than the drift region; forming a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on a surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and forming a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from the surface of the device.

47. A method according to claim 46, further comprising forming a first semiconductor region of the second conductivity type between the semiconductor substrate and the semiconductor drift region.

48. A method according to claim 46 or 47, wherein the semiconductor region within the drift region is a second semiconductor region.

49. A method according to any one of claims 46 to 48, wherein forming the lateral extension comprises applying a two stage photo-masking to implant the lateral extension.

50. A method according to any one of claims 46 to 49, wherein the lateral extension is ion-implanted using Aluminium or Boron material.

51. A method according to any one of claims 46 to 50, further comprising vertically spacing the lateral extension from the surface of the device.

52. A method according to any of claims 48 to 51, further comprising forming an ohmic contact on the second semiconductor material, the ohmic contact comprising titanium disilicide material.

53. A method according to any one of claims 46 to 52, further comprising forming a Schottky metal contact directly on the drift region.

54. A method according to claim 53, further comprising forming the Schottky contact using a relatively low temperature compared to that used for forming the ohmic contact, the Schottky contact comprising nickel material.

55. A method according to any one of claims 48 to 54, further comprising forming the semiconductor substrate using a material comprising monocrystalline silicon, and forming each of the semiconductor drift region, the first semiconductor region, the lateral extension and the second semiconductor region using a material comprising 3-step cubic silicon carbide (3C-SiC).

56. A method according to any one of claims 48 to 54, further comprising forming each of the semiconductor substrate, the first semiconductor region, the semiconductor drift region, the lateral extension and the second semiconductor region using a material comprising 4H-SiC.

57. A method according to any one of claims 48 to 54, further comprising forming each of the semiconductor substrate, the first semiconductor region, the semiconductor drift region, the lateral extension and the second semiconductor region using a material comprising GaN.

58. A method according to any one of claims 48 to 54, further comprising forming the semiconductor substrate using monocrystalline silicon material, and forming each of the first semiconductor region, the semiconductor drift region, the lateral extension and the second semiconductor region using a material comprising GaN.

59. A method according to any one of claims 48 to 54, further comprising forming the semiconductor substrate using SiC material, and forming each of the first semiconductor region, the semiconductor drift region, and the second semiconductor region using a material comprising GaN.

60. A method for manufacturing a wide band-gap high voltage semiconductor transistor, the method comprising: forming a semiconductor substrate; forming a semiconductor drift region of a second conductivity type on the semiconductor substrate; forming a body region of a first conductivity type, opposite the second conductivity type, located within the semiconductor drift region; forming a lateral extension of the first conductivity type extending laterally from the body region into the drift region, the lateral extension being spaced from the surface of the transistor; forming a source region of the second conductivity type located within the body region; forming a gate placed above and in contact to the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region.

61. A method according to claim 60, wherein forming the lateral extension comprises applying a two stage photo-masking to implant the lateral extension.

62. A method according to claim 60 or 61, wherein the lateral extension is ion-implanted using Aluminium or Boron material.

63. A method according to claim 60, 61, or 62, further comprising vertically spacing the lateral extension from the surface of the transistor.

64. A method according any of claims 60 to 63, further comprising forming a first semiconductor region between the semiconductor substrate and the drift region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.

[0090] FIG. 1 illustrates a prior art Si based device in which floating field rings are formed to reduce curvature effect;

[0091] FIG. 2 illustrates a prior art Si based device in which junction termination structures are formed to reduce curvature effect;

[0092] FIG. 3 illustrates a schematic cross section of a vertical MOSFET located adjacent to a termination region of the MOSFET;

[0093] FIG. 4 illustrates a schematic cross section of an alternative vertical MOSFET located in an active region of the MOSFET;

[0094] FIG. 5 illustrates a schematic cross section of a vertical IGBT located adjacent to a termination region of the IGBT;

[0095] FIG. 6 illustrates a schematic cross section of an alternative vertical IGBT located in an active region of the IGBT;

[0096] FIG. 7 illustrates a schematic cross section of a vertical PIN diode;

[0097] FIG. 8 illustrates a schematic cross section of a termination structure; and FIG. 9 illustrates a schematic cross section of a vertical Schottky diode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0098] Referring to FIG. 3, an example of a SiC based vertical power semiconductor transistor 100 in the form of a metal-oxide-semiconductor field effect transistor (MOSFET) is shown. The transistor 100 is an active transistor which can be arranged as the last active transistor among an array of transistors which is located adjacent a termination region. A highly doped n-type layer (or the first semiconductor region) 120 is formed on an n-type substrate 110. A drift region 130 is formed on the first semiconductor 120. A p-type well 140 is formed within the drift region 130. An n-type highly doped source region 150 is formed within the p-type well region 140. A p-type highly doped region is formed within the p-type well 140. The highly doped p and n type regions 150, 155 are shorted using a source contact or electrode 185. A field oxide or insulator 195 is also formed adjacent the highly doped p-type region 155 and the source contact extends over the field oxide 195. The extended source contact 185 is generally termed as a field plate. The P-type well 140 at the surface 160 of the epitaxial layer or the drift region 130 provides a body region. The N-type well 150 within the p-type wells 140 provides a contact region and provides a source. A channel 170 is formed beneath a gate 180 which is separated using a gate dielectric layer 190.

[0099] The MOSFET 100 also includes a lateral extension region 145 extending from the body region 140. The lateral extension 145 extends laterally from the lower part of the body region 140 into the drift region 130. The lateral extension 145 is formed using ion implantation together with two stage photo-masking to extend the lower part of the junction laterally. This lower implant is optimised in terms of dose and dimensions and is combined with an optimised field oxide 195 thickness and metal field plate 185. The lateral extension 145 extends towards the direction to which the field plate 185 extends over the field oxide 195 adjacent the source region. Generally the lateral extension 145 extends further/more than the field plate 195 extension. The lateral extension 145 allows higher breakdown voltage (Vbr) to be achieved than theoretical limits predict for the given doping level. Due to the presence of the lateral extension 145, a vertical p-n junction is formed between the upper surface 145a of the lateral extension and the drift region 130 which reduces peak electric field (EF). This structure is different from existing solutions which use lateral p-n junctions to achieve a similar result. A further vertical p-n junction is formed by the lower surface 145b of the lateral extension 145 and the drift region 130. This p-n junction can also contribute to achieve higher breakdown voltage.

[0100] The p-type body region 140 can have two portions. The first portion is the top portion in which the channel region 170 is formed. The highly doped p region 155 is also formed in the top portion of the body region 140. The top portion includes relatively higher doping concentration. The second portion is below the top portion and therefore is deeper than the top portion. The deeper portion includes relatively less doping concentration than the top portion. The lateral extension 145 is extended from the deeper portion of the body region 145. The doping concentration of the lateral extension is generally substantially the same as the doping concentration of the deeper portion of the body region 145. The doping concentration of the lateral extension is generally about 10.sup.16 cm.sup.−3 to 10.sup.18 cm.sup.−3, preferably about 10.sup.17 cm.sup.−3 The lateral extension 145 is formed in such a way that there is a vertical space between the lateral extension 145 and the surface 160 of the device. In one example, the vertical space between the lateral extension 145 and the surface 160 of the device is about 0.05 μm to 0.6 μm, preferably about 0.1 μm.

[0101] The proposed lateral extension 145 (deep p-implant) can also help to reduce the peak electric field in the active area (e.g. in the drift region 130), at the top portion of the body region 140 and drift region junction (p+/n-epi junction) at the surface 160 of the device. Generally, in a conventional device, high drift region (n-epi) doping and p+ body region (in the top portion of the body region) curvature can lead to a higher electric field (EF) at the edge of the p+ body compared to the electric field (EF) at the vertical p+ body/n-epi junction in the active area of the device (when there is no lateral extension present in the structure). Lowering the drift region (n-epi) doping is not always possible and without it, the maximum achievable breakdown voltage (Vbr) will be limited by the curvature of the p+/n-epi junction. Using this lowly doped deep p-implant 145, or the lateral extension 145, as an extension of the body region 140 in the active area too, the peak electric field (EF) can be reduced leading to an increased breakdown voltage of the device (providing that the breakdown voltage in the termination is always higher than in the active region). The lateral extension 145 is formed by ion implantation of the aluminum material which is fully compatible in wide band-gap material (e.g. SiC) based fabrication techniques.

[0102] It will be appreciated that in the example of FIG. 3 the p-type lateral extension 145 is used near the termination region of the high voltage device. The lateral extension 145 may be implanted in devices which are located near the perimeter, outside or outer devices of an array of devices. The devices located in the central portion of the array may not have such lateral extension 145 structures. In the example of FIG. 3, the lateral extension structure 145 generally extends laterally into the drift region in a direction which is opposite to the direction to which the gate extends from source to the drift region. In other words, the lateral extension 145 is generally not below the channel region 170 in the device in the example of FIG. 3.

[0103] The transistor of FIG. 3 can be manufactured using a wide band-gap semiconductor material, for example, SiC, GaN and/or diamond. In one embodiment, the substrate 110, the first semiconductor layer 120, the drift region 130, the body region 140, the lateral extension 145, the source region 150 each include 4H-SiC material. Alternatively, the substrate 110 can include silicon material and the remaining regions can have 3C-SiC material. In this particular example, the MOSFET shown in FIG. 3 is able to support much greater breakdown voltages due to the use of 3C-SiC in the epitaxial drift region 130. At the same time the on-resistance of the 3C-SiC MOSFET can be significantly lower than the 4H-SiC MOSFET. This is because a better channel mobility is observed in 3C-SiC (compared to 4H-SiC) and therefore the on-resistance of the channel region formed between the drift region 130 and the source region 150 can be significantly reduced. It will be appreciated that, in an alternative embodiment, the substrate 110 can include GaN and the remaining regions can have GaN as well. It is also possible that the substrate includes silicon material and the remaining regions each include GaN. In one embodiment, the substrate 110 can include SiC and the remaining regions can each include GaN.

[0104] It will be appreciated that the first semiconductor region/layer 120 has two purposes: (1) it acts as a buffer layer between the substrate 110 and the drift region 130 to form a punch-through structure so that during the off-state operation the depletion region does not contact the substrate 110 from the drift region 130; (2) it reduces the interface defects between the substrate which is typically made of Silicon material and drift region 130 which is typically made of a wide band gap material such as 3C-SiC, 4H-SiC or GaN.

[0105] Referring to FIG. 4, an alternative example of a vertical power MOSFET is shown.

[0106] Many features of the MOSFET of FIG. 4 are the same as the MOSFET of FIG. 3 and therefore carry the same reference numbers. However, the MOSFET of FIG. 4 is an active transistor located in an active region of an array of MOSFETs on a chip. The lateral extension 145 of the transistor of FIG. 4 extends into the drift region 130 towards the gate 180. In other words, the lateral extension 145 is formed under the channel region of the MOSFET. The operation and features of the MOSFET of FIG. 4 are substantially the same as the operation of the MOSFET of FIG. 3

[0107] Referring to FIG. 5, an example of a vertical power semiconductor transistor 200 in the form of an insulated gate bipolar transistor (IGBT) is shown. Many features of the IGBT in FIG. 5 are the same as the MOSFET of FIG. 3 and therefore carry the same reference numerals, except the IGBT 200 includes a p+ type substrate 215 and a p+ type collector layer or the first semiconductor region 225. The first semiconductor region 225 forms a carrier injector region in the IGBT. It will be appreciated that the off-state operation of the IGBT 200 is substantially similar to that of the MOSFET 100 of FIG. 3. In the off-state, the vertical junctions 145a, 145b between the lateral extension and drift region 130 help to reduce the peak electric field at the surface 160 of the device. Therefore the p-lateral extension 145 in the IGBT can act as a termination structure in the device. The doping concentration of the lateral extension 145 is substantially the same as that described for the MOSFET structure 100 in FIG. 1. The vertical distance between the p-lateral extension 145 and the surface 160 of the device is also substantially the same as the MOSFET 100 of FIG. 3. In this example, the IGBT of FIG. 5 is an active transistor which can be arranged as the last transistor among an array of transistors and the active transistor of FIG. 5 can be located adjacent a termination region.

[0108] In one embodiment, all the layers of the IGBT can have 4H-SiC. Alternatively, the p+ substrate can be made of silicon and the remaining layers can include 3C-SiC. It will be appreciated that a hetero-structure is formed between the p+ silicon substrate 215 and p+3C-SiC layer 225. The 3C-SiC material in the first semiconductor (epitaxial) region 225 (˜2 microns) just above the SiC/Si interface is very heavily defective because of the lattice miss-match between the two materials and heavily doped with Al as-grown, consequently this defective region is very conductive. In this way the heterojunction structure and consequent potential barriers can be overcome by becoming a quasi-metallic interface due to the presence of the dislocations, Al doping during epitaxial growth and Boron up-diffusion from the Si substrate. It will be appreciated that, in an alternative embodiment, the substrate 215 can include GaN and the remaining regions can have GaN as well. It is also possible that the substrate 215 includes silicon material and the remaining regions each may include GaN. In one embodiment, the substrate 215 can include SiC and the remaining regions each may include GaN. Referring to FIG. 6, an alternative example of a vertical power IGBT is shown. Many features of the IGBT of FIG. 6 are the same as the IGBT of FIG. 5 and therefore carry the same reference numbers. However, the IGBT of FIG. 5 is an active transistor located in an active region of an array of IGBTs on a chip. The lateral extension 145 of the transistor of FIG. 6 extends into the drift region 130 towards the gate 180. In other words, the lateral extension 145 is formed under the channel region and the accumulation region (adjacent the channel region) of the IGBT. The operation and features of the IGBT of FIG. 6 are substantially the same as the operation of the IGBT of FIG. 5. A further difference between the IGBTs of FIGS. 5 and 6 is that it includes an n-type buffer layer 265 between the drift region 130 and the first semiconductor region 225. The buffer layer 265 stops the depletion region from the drift region 130 to extend to the first semiconductor region 225 during the off-state operation of the device.

[0109] Referring to FIG. 7, an example of a vertical PIN diode 700 is shown. The PIN diode 700 includes a substrate 710 on which an n-type epitaxial layer (or the first semiconductor region) 720 is formed to provide a cathode contact. An n-type lowly doped drift region 730 is formed on the n-type epitaxial layer 720. A p+ doped region 750 formed in the drift region 730 and forms an anode contact region 770. The anode contact 770 extends over a field oxide 780 to form a field plate. A lateral extension 745 is formed from the deeper part of the p+ doped region 750 extending laterally into the drift region 730. The doping concentration adjacent the area of the lateral extension 745 and the p+ doped region can be slightly higher than the doping concentration of the drift region. In other words, a region having a slightly higher doping than the drift region can be formed adjacent the lateral extension 745 and the p+ doped region 750. In one example, the doping concentration of the region next to the lateral extension and p+ doped region is generally about above 10.sup.16 cm.sup.−3 and the doping concentration of the drift region is about 10.sup.15 cm.sup.−3. The doping concentration of the lateral extension 745 is about 10.sup.17 cm.sup.−3.

[0110] In the off-state, the lateral extension 745 operates in the same way as described above in respect of the MOSFETs and IGBTs above. The vertical junctions between the lateral extension 745 and the drift region 730 helps to reduce the peak electric field at the surface of the device which is otherwise created due to the curvature of the p+ doped region 750 at the surface of the device. The field plate also helps to reduce the peak electric field at the surface of the device. Similar to the embodiments described above, the substrate 710 can include silicon material and the remaining layers can include 3C-SiC. Alternatively, all the layers of the PIN diode 700 can be made of 4H-SiC. Yet alternatively, the substrate 215 can include GaN and the remaining regions can have GaN as well. It is also possible that the substrate 215 includes silicon material and the remaining regions each include GaN. In one embodiment, the substrate 215 can include SiC and the remaining regions each may include GaN. It will be appreciated that the first semiconductor region 720 acts as a buffer layer which prevents the depletion region to extend from the drift region 730 to the substrate 710. The first semiconductor layer 720 also acts to reduce the defects in the interface between the substrate 710 and the first semiconductor region 720.

[0111] In one example, the diode of FIG. 7 is a discrete diode or part of an array of diodes. In a further example, the diode of FIG. 7 can be located in a termination region of any of the devices described in FIGS. 3 to 6.

[0112] FIG. 8 illustrates an example of a termination structure 800 of a power semiconductor region in which lateral extensions according to the present invention are provided. Many features of FIG. 8 are the same as the features of FIG. 7 and therefore carry the same reference numbers. However, the termination structure of FIG. 8 includes floating guard rings 885 laterally distant from the p+ doped region 750. The field plate and field oxide of FIG. 7 are missing in FIG. 8, but it would be appreciated that these features can generally be present in the termination structure of FIG. 8. P-type lateral extensions 890 are extended into the drift region 730 from the lower part of the floating guard rings 885. The existence of the lateral extensions 890 from the floating guard rings 885 improves the breakdown voltage in the termination region. The termination structure 800 of FIG. 8 can be used in the termination region of the devices described above with reference to FIGS. 3 to 7.

[0113] Referring to FIG. 9, an example of a vertical Schottky diode 900 is shown. The Schottky diode 800 includes a substrate 810 on which an n-type epitaxial layer (or the first semiconductor region) 820 is formed to provide a cathode contact. Both the substrate 810 and the n-type epitaxial layer 820 are highly doped and thus the cathode contact is an ohmic contact. An n-type lowly doped drift region 830 is formed on the n-type epitaxial layer 820. A highly doped p+ doped region 850 (or the second semiconductor region) is formed within the drift region 830. A local anode ohmic metal contact 855 over the p+ doped region 850 is firstly formed using a high temperature. After this, a Schottky anode metal contact 865 is formed directly on the drift region 830. The Schottky contact 865 is formed using a relatively lower temperature compared to the temperature used for forming the ohmic contact on the p+ doped region 850. The Schottky anode contact 865 may be made of Nickel and the ohmic anode contact 855 may be made of titanium disilicide (TiSi2), although other suitable materials may be used. It will be appreciated that TiSi2 may be used when the Schottky diode uses 3C-SiC material. Furthermore, an Aluminium contact (not shown) is formed on the Schottky contact 865 and the ohmic contact 855 to short these together and to form a high conductivity connection layer. It will be appreciated that both the ohmic contact 855 and the Schottky contact 865 can be made using the same material.

[0114] In FIG. 9, a lateral extension 845 is formed from the deeper part of the p+ doped region 850 extending laterally into the drift region 830. The p+ doped region 850 is used to connect to a guard ring structure. At high voltage/current the p+ doped region 850 forward biases and conductivity modulates the drift region 830, reducing its resistance and moderating the power dissipated. This is advantageous for a robust power component. The lateral extension 845 extends under the edges of the Schottky contact 865 to act as a shield in a reverse bias operation. In one example, the length of the Schottky contact 865 can be about 8 μm. In alternative example, the length of the Schottky contact 865 can be about 2 μm to 40 μm, preferably about 5 to 15 μm. The length of the lateral extension 845 towards the Schottky contact 865 can be about 2 μm. In an alternative embodiment, the length of the lateral extension 845 (after the p+ doped region 850) can be about 0 μm to 100 μm, preferably about 0 μm to 40 μm (depending on the application of the device). The diode structure 900 includes two regions: (1) a PIN diode region 860 just underneath p+ doped region 850 and the lateral extension region 845, (2) a Schottky diode region 870 underneath the Schottky contact 865. The combined effect of PIN diode and Schottky diode in the structure 900 of FIG. 9 helps to turn-on the device in a relatively low voltage (about 0.1 V) and achieves a higher current without turning into a saturation region of the device characteristics.

[0115] In the structure of FIG. 9, all the layers can include silicon material. Alternatively, it is possible that the substrate 810 has silicon material and the remaining layers have 3C-SiC material. It may be also possible that all the regions of the diode 900 have 4H-SiC material. Other wide band-gap semiconductor materials such as GaN or diamond are possible to use. For example, all the regions of the diode may have GaN material. Alternatively, the substrate may have SiC material and the remaining layers may have GaN. Yet alternatively, the substrate 810 may have silicon material and the remaining layers may have GaN.

[0116] In one embodiment, when the all the layers of the diode of FIG. 9 comprise Silicon material, the semiconductor layer 820 acts as a buffer layer which mainly stops the depletion from extending to the substrate 810 in a punch-through arrangement. In such an arrangement, the buffer layer 820 can be optional.

[0117] In a further embodiment, when the substrate 810 comprises Silicon material and the rest of the layers comprise a wide bandgap material such as SiC, the first semiconductor layer 820 also acts to reduce the interface defects between the silicon substrate 810 and the SiC first layer 820. In such an arrangement, the first semiconductor layer 820 is generally provided in the structure (even though it is not a punch through arrangement).

[0118] Although the aforementioned description states the use of mainly SiC and GaN, it would be apparent to the skilled person that other polytypes of wide band-gap semiconductor materials can be equally used in the devices described above.

[0119] Although the aforementioned description illustrates mainly vertical semiconductor device, it would be appreciated that the lateral extensions can be used in lateral power devices as well, such as lateral MOSFETs, IGBTs and diodes. In lateral devices, the lateral extensions would be used as interconnects and/or insulating means from the surrounding low voltage devices. It will be also appreciated that the lateral extension disclosed above can also be used in a lateral-high-electron-mobility-transistor (HEMT) using GaN material.

[0120] It will be appreciated that the lateral extension can be introduced in a wide band-gap semiconductor based thyristor, a gate turn-off (GTO) thyristor, a gate-commutated thyristor (GCT), and/or a bipolar junction transistor (BJT). It will be appreciated that the layout of the lateral extension extending to the drift region is not limited to what has been presented as hereinbefore as long as the concept is the same.

[0121] It will also be appreciated that terms such as “top” and “bottom”, “above” and “below”, “lateral” and “vertical”, and “under” and “over”, “front” and “behind”, “underlying”, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied.

[0122] It will be appreciated that the doping concentrations of various layers of the transistors discussed with reference to FIGS. 3 to 9 are those used in the corresponding state of the art transistors.

[0123] It will be noted that the term “first conductivity type” can refer to a p-type doping polarity and the term “second conductivity” can refer to an n-type doping polarity. However, these terms are not restrictive. It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. It will be appreciated that the emitter, collector and gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.

[0124] Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.