A semiconductor device that can be highly integrated is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer. The semiconductor layer includes a first portion overlapping with the first insulating layer, a pair of second portions between which the first portion is sandwiched and which overlap with the second insulating layer, and a pair of third portions between which the first portion and the pair of second portions are sandwiched and which overlap with neither the first insulating layer nor the second insulating layer. The first portion has a smaller width than the first opening and has a thinner shape of the semiconductor layer than the second portions, and the second portions have a thinner shape of the semiconductor layer than the third portions.

An oxide thin film transistor includes an oxide active layer, a first loose layer and a first oxygen release layer. The first loose layer is at least disposed on a first surface of the oxide active layer perpendicular to a thickness direction of the oxide active layer, and is in contact with the oxide active layer. A material of the first loose layer includes a first inorganic oxide insulating material. The first oxygen release layer is disposed on a surface of the first loose layer facing away from the oxide active layer, and is in contact with the first loose layer. A material of the first oxygen release layer is a first oxygen-containing insulating material.

A display device includes: a substrate; a semiconductor layer; a gate electrode overlapping the semiconductor layer; a common voltage line disposed on a same layer as the gate electrode; a common voltage line anti-oxidation layer disposed on the common voltage line; an interlayer insulating layer; source and drain electrodes disposed on the interlayer insulating layer; and a common voltage applying electrode disposed on a same layer as the source electrode and the drain electrode. The common voltage applying electrode is connected to the common voltage line through a first contact hole formed in the interlayer insulating layer, the common voltage line anti-oxidation layer includes an opening overlapping the common voltage line, the interlayer insulating layer is disposed in the opening, a width of the opening is smaller than a width of the common voltage line, and the first contact hole is disposed in the opening in a plan view.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

A display device is provided. The display device includes a substrate, a first active layer of a first transistor and a second active layer of a second transistor which are disposed on the substrate, a first gate insulating layer disposed on the first active layer, an oxide layer disposed on the first gate insulating layer and including an oxide semiconductor, a first gate electrode disposed on the oxide layer, a second gate insulating layer disposed on the first gate electrode and the second active layer, and a second gate electrode which overlaps the second active layer in a thickness direction of the substrate and is disposed on the second gate insulating layer, where the oxide layer overlaps the first active layer and does not overlap the second active layer in the thickness direction.

A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

Provided are a ferroelectric material and an electronic device including same, the ferroelectric material including: a first domain including a first polarization layer which is polarized in a first direction and a first spacer layer disposed adjacent to the first polarization layer; a second domain including a second polarization layer which is polarized in a second direction distinct from the first direction and a second spacer layer disposed adjacent to the second polarization layer; and a structural layer, which is disposed at a domain wall between the first domain and the second domain, and belongs to/has atoms arranged according to a Pbcn space group.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.