SEMICONDUCTOR STRUCTURE WITH NANOFOG OXIDE ADHERED TO INERT OR WEAKLY REACTIVE SURFACES

Abstract

A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2. Additional examples are from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.

Claims

1. A semiconductor structure comprising a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al.sub.2O.sub.3 nanoparticles.

2. The semiconductor structure of claim 1, wherein the surface is an unfunctionalized surface.

3. The semiconductor structure of claim 1, comprising an oxide layer on the nanofog oxide.

4. The semiconductor structure of claim 3, wherein the oxide layer is Al.sub.2O.sub.3.

5. The semiconductor structure of claim 3, wherein the oxide layer is HfO.sub.2.

6. The semiconductor structure of claim 3, wherein the oxide layer is selected from the group consisting of ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, Gd.sub.3Ga.sub.5O.sub.12, and alloys thereof, including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2

7. The semiconductor structure of claim 1, wherein the inert surface comprises a 2D semiconductor substrate.

8. The semiconductor structure of claim 7, wherein the 2D semiconductor substrate is selected from the group consisting of graphene, HOPG (Highly oriented pyrolytic graphite), and TMDs (transition metal dichalcogenides).

9. The semiconductor structure of claim 8, wherein the TMDs are MoS.sub.2, WeSe.sub.2,

10. The semiconductor structure of claim 1, wherein the inert surface is the surface of a 3D material.

11. The semiconductor structure of claim 10, wherein the 3D material is selected from the group consisting of nanowires and nanotubes.

12. The semiconductor structure of claim 1, wherein the weakly reactive metal surface is selected from the group consisting of Pt, Au, and Ru.

13. The semiconductor structure of claim 1, in a metal-insulator-metal capacitor, wherein the inert 2D surface is a surface selected from the group of HOPG and MoS.sub.2 substrates, comprising an oxide layer of Al.sub.2O.sub.3 on the nanofog oxide and a metal gate formed on the oxide layer.

14. The semiconductor structure of claim 13, wherein the oxide layer comprises a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2.

15. The semiconductor structure of claim 1, in a field effect transistor, the transistor comprising: a semiconductor substrate with a dielectric layer, gate electrodes isolated from each other by nanolaminate oxide comprising the nanofog oxide and an oxide layer with one of the gate electrodes contacting the semiconductor substrate and the other being isolated from the semiconductor substrate by the nanolaminate oxide; high-K dielectric formed on the nanolaminate oxide; and source and drain contacts upon the high-K dielectric, one of the source and drain contacts also contacting the nanolaminate oxide.

16. The semiconductor structure of claim 15, wherein the oxide layer comprises a bilayer stack of Al.sub.2O.sub.3— HfO.sub.2.

17. The semiconductor structure of claim 1, in a metal oxide semiconductor capacitor, the capacitor comprising a substrate defining the inert 2D surface, an oxide layer on the nanofog oxide and a multilayer metal top gate.

18. The semiconductor structure of claim 17, wherein the substrate is selected from the group consisting of MoS.sub.2, HOPG, and SiGe,

19. The semiconductor structure of claim 18, wherein the oxide layer comprises a bilayer stack of Al.sub.2O.sub.3—HfO.sub.2.

20. The semiconductor structure of claim 1, wherein the nanofog oxide consists essentially of sub 1 nm Al.sub.2O.sub.3 nanoparticles.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIGS. 1A-1C are AFM images of Al.sub.2O.sub.3 films (50 ALD cycles) on HOPG with respective sample growth temperatures of 200° C., 150° C. and 50° C., and FIG. 1D is an AFM image of 50 ALD cycles of Al.sub.2O.sub.3 deposited with 2 s purge times at sample temperature of 50° C., using otherwise identical ALD conditions as for the samples in FIG. 1A;

[0010] FIGS. 2A-2C are AFM images of Al.sub.2O.sub.3 films (50 ALD cycles) on (a) MoS.sub.2, (b) HOPG (c) Si.sub.0.7Ge.sub.0.3 (001) grown at 50 C sample temperature;

[0011] FIGS. 2D-2F are line profiles taken along the dotted lines in FIGS. 2A-2C, respectively;

[0012] FIGS. 3A-3C are a comparison of Electrical Properties of Low Temperature Al.sub.2O.sub.3ALD on HOPG and Si.sub.0.7Ge.sub.0.3 (001) with cycles consisting of a 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge at 50° C. sample temperature;

[0013] FIG. 4 is a cross-sectional schematic diagram of a dual bottom gated Field Effect Transistor to which the present ALD method was employed to form nanolaminate gate oxides (the device structure and diagram are from the lab of Prof Zhihong Chen of Purdue, and the structure was used to test dielectrics of the present invention); and

[0014] FIGS. 5A-5C are capacitance vs. voltage curves of Pd/Ti/TiN/Low temperature Al.sub.2O.sub.3 (10 ALD cycles)+HfO.sub.2 (40 ALD cycles) on (FIG. 5A) MoS.sub.2, (FIG. 5B) HOPG, (FIG. 5C) Si.sub.0.7Ge.sub.0.3 (001) stacks; FIGS. 5D-5F are leakage currents of Pd/Ti/TiN/Low temperature Al.sub.2O.sub.3 (10 ALD cycles)+HfO.sub.2 (40 ALD cycles) on (FIG. 5D) MoS.sub.2, (FIG. 5E) HOPG, (FIG. 5F) Si.sub.0.7Ge.sub.0.3 (001) stacks

[0015] FIGS. 6A and 6B are AFM images of 50 cycle of Al.sub.2O.sub.3 films on bulk MoS.sub.2 with different purge times that demonstrate sub 1 nm surface roughness created by Al.sub.2O.sub.3 nanoparticles.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The invention overcomes limitations and disadvantages of prior techniques discussed in the background. The invention provides ALD techniques that enable the deposition of thin and uniform gate dielectric layers, bilayers and multilayers. In accordance with preferred embodiments, gate dielectric layers can be directly deposited on 2D semiconductor surfaces by low temperature ALD without any functionalization methods prior to deposition; In contrast to previous work, ALD can be performed on three dimensional structures and bilayer layer high-K oxide can be deposited. Controlling the pulse times of TMA and H.sub.2O along with a short purge time, 1-2 and sub 1 nanometer diameter spherical Al.sub.2O.sub.3 nanoparticles are formed on HOPG, TMDs, SiGe, and weakly reactive metal surfaces consistent with a gas phase reaction of the ALD precursors. With optimized conditions, the formed nanofog of Al.sub.2O.sub.3 nanoparticles can consist essentially of sub 1 nm nanoparticles. The nuclei provided uniform nucleation centers on the inert 2D semiconductors surface resulting in uniform and pin-hole free Al.sub.2O.sub.3 films on both step edges and terraces. This Al.sub.2O.sub.3 layer can be used as a seeding layer for ALD of an HfO.sub.2 layer or other high-k oxide which can be deposited at higher temperature and which can be added to provide higher dielectric constant. Preferred high-K oxides include ZrO.sub.2, HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2, ZrTiO.sub.2, HfTiO.sub.2, La.sub.2O.sub.3, Y.sub.2O.sub.3, Ga.sub.2O.sub.3, Gd.sub.3Ga.sub.5O.sub.12, and alloys of these, etc., including the ferroelectric phases of HfZrO.sub.2, silicon or other doped HfO.sub.2 or ZrO.sub.2. In making such a bilayer or multi-layer stack of high-K oxide/Al.sub.2O.sub.3, high quality oxides with lower EOT values can be achieved. Further lowering of the EOT can be achieve using a remote gettering gate. For 3D object, a rotation during the Al.sub.2O.sub.3 layer deposition may be needed to insure uniform coverage. Nearly any other gates oxide or selector oxide could be deposited at the usual high temperature via ALD on the Al.sub.2O.sub.3 seed layer.

[0017] The invention overcomes limitations and disadvantages prior techniques discussed in the background. This invention provides methods to deposit high-k gate dielectrics via atomic layer deposition (ALD) on 2D semiconductor substrates (including graphene, HOPG (Highly oriented pyrolytic graphite), and TMDs (transition metal dichalcogenides) such MoS.sub.2WSe.sub.2, of 3D version of 2D semiconductor such as nanotube, and other inert 2D or 3D surfaces such as weakly reactive metals directly upon without any surface treatments or seeding layers (such as metallic Al or O.sub.3 or NO.sub.x). This ALD technique ALD can be directly applied upon any 2D or 3D semiconductors to deposit very thin gate oxides stacks because the gas phase formation of nano-nuclei is not dependent on the surface. This invention can also be applied to inert metals or weakly reactive such metals such as Pt, Au, Ru, etc., which can be used as the substrate film for a selector in memory devices. This invention can also be used as a general process to obtain a quality oxide layer for semiconducting devices such as FETs, tunnel devices, threshold switch, memory cell, solar cells and etc. An example is selector devices for Resistive RAM.

[0018] In this invention, ALD of uniform and insulating gate dielectric films can be achieved on any 2D semiconductors or 3D structures (3D may require substrate rotating), including inert surfaces or weakly reactive surfaces without an ALD induction period prior to onset of uniform film growth. In addition, preferred methods remove the need for the surface functionalization processes of 2D semiconductors (or inert surface or weakly reactive surface) prior to ALD enabling more efficient fabrication of 2D semiconductor devices (or a device such as a selector on an inert surface or weakly reactive surface).

[0019] Preferred embodiments provide a method for depositing high-k gate dielectrics via atomic layer deposition (ALD) on 2D semiconductor substrates (including graphene, HOPG, and TMDs such MoS.sub.2) and other inert surfaces (including 3D materials) such as weakly reactive metals without any surface treatments or seeding layers (such as metallic Al or O.sub.3 or NO.sub.x). The gate dielectrics can consist of Al.sub.2O.sub.3 only or Al.sub.2O.sub.3 incorporated at the bottom of HfO.sub.2 or other high-k as listed above which have higher dielectric constants. Al.sub.2O.sub.3 can be directly deposited on 2D semiconductors surfaces by low temperature thermal ALD using trimethylaluminum (TMA) and H.sub.2O. With the substrates in a temperature range of 25° C. to 80° C. with 50° C. being optimal in the ALD system employed for the tests, using short purge times between the two precursor pulses and long pulses of the precursors, a CVD growth component was intentionally employed to provide more nucleation sites on the surface. The CVD growth component induces formation of 0.5-2 nanometer Al.sub.2O.sub.3 particles (a nanofog) on the surface which provide nucleation centers for uniform deposition. The nanofog of sub 1 nm Al.sub.2O.sub.3 particles sticks to even the most inert known surfaces, e.g., graphene and HOPG, even in the absence of defects and are sufficiently reactive to nucleate subsequent ALD at high temperatures. The Al.sub.2O.sub.3 film deposited by this method is continuous and uniform without defects. For 3D dimensional 2D semiconductors (nanowires, nanotubes, etc), a uniform coverage of oxide can be deposited around structure by rotation of the substrate at least once during Al.sub.2O.sub.3 ALD.

[0020] In preferred methods demonstrated experimentally, prior to ALD, 2D experimental semiconductor samples are cleaned by the mechanical exfoliation method using an adhesive tape or they are cleaned via heating in UHV to remove photoresist if they are CVD or MBE grown. Commercially synthesized 2D semiconductors are grown by chemical vapor deposition (CVD), chemical vapor transport, or molecular beam epitaxy (MBE); in the future ALD may be used. This produces 1-10 monolayer films. Exfoliation is only for bulk thick materials and of not of commercial interest. Gate dielectric layers can be deposited in a low vacuum (torr) continuous crossflow chamber but other configurations (showerhead and UHV are possible). Metal surfaces are cleaned by cyclic cleaning with acetone, IPA and Water. To deposit Al.sub.2O.sub.3, TMA and H.sub.2O are used as ALD precursors, temperature stabilized at 20° C. The carrier gas can be research purity argon. ALD is employed, each cycle consisting of a sequence of 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge. The pulse lengths depend on ALD chamber geometry and size but have shorter purge times and longer pulse times than typical purely ALD TMA reactions at the same temperature. HfO.sub.2 or other high-k ALD can be performed subsequently using a wide variety of Hf precursors including hafnium tetrachloride (HfCl.sub.4) and Tetrakis(dimethylamido)hafnium (TDMAH) at high temperature since the low T Al.sub.2O.sub.3 layer acts as a nucleation layer for the standard HfO.sub.2 process. HfO.sub.2 ALD is performed by cyclic pulsing of TDMAH or HfCl.sub.4 and H.sub.2O in a continuous cross-flow ALD chamber with base pressure of 1.5-2 torr with the substrates temperature over 200° C.

[0021] Gettering can also be leveraged to improve dielectric properties. Preferred methods, for example, form an oxygen scavenging metal on a defect free and uniform Al.sub.2O.sub.3 layer or forming an oxygen scavenging metal on top of a bilayer stack of nanofog Al.sub.2O.sub.3 layer plus a high-k dielectric layer, or a remote gettering gate of Pd/Ti/TiN or another remote gettering material, on top of the nanofog Al.sub.2O.sub.3 layer or on top of a high-k dielectric layer on the nanofog Al.sub.2O.sub.3 layer.

[0022] Preferred ALD techniques at low temperature are of particular interest on 2D semiconductors. (1) Deposition of uniform and insulating gate dielectric films can be achieved on any 2D semiconductors without an ALD induction period prior to onset of uniform film growth. (2) Using preferred methods, it is possible to obviate the need for surface functionalization processes of 2D semiconductors which are typically performed prior to ALD enabling more efficient fabrication of 2D semiconductor devices and no damage to the substrate. This preferred two-step ALD technique can also be applied, for example, to inert metal surfaces to grow oxide, which can be important for a variety of devices including selectors for memory chips.

[0023] Preferred embodiments of the invention will now be discussed with respect to the drawings and experiments. The drawings may include schematic representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows. Features may be exaggerated in the drawings for emphasis, and features may not be to scale.

[0024] In order to evaluate the oxide quality of oxides formed according to the invention, Metal-Oxide-Semiconductor capacitors (MOSCAPs) were fabricated with HOPG ((Highly oriented pyrolytic graphite), MoS.sub.2 and Si.sub.0.7Ge.sub.0.3 substrates. HOPG and MoS.sub.2 samples were cleaned by the mechanical exfoliation method using an adhesive tape. The samples were loaded into a commercial ALD reactor (Beneq TFS 200 ALD system) which has a hot wall, crossflow reaction chamber. The reaction chamber was pumped down to 1 mTorr. To deposit Al.sub.2O.sub.3, TMA and H.sub.2O were used as ALD precursors, temperature stabilized at 20° C. The carrier gas was research purity argon (Ar, Praxair, 99.9999%) which was flowed at 300 sccm (standard cubic centimeter). 50 cycles of ALD were employed, each cycle consisting of a sequence of 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge. For comparison, using identical ALD pulse times, films were grown with sample temperatures between 50° C. to 200° C. to investigate the effect of temperature on the nucleation of Al.sub.2O.sub.3. To compare nucleation behavior on a highly reactive substrate, Al.sub.2O.sub.3 was deposited on Si.sub.0.7Ge.sub.0.3 (001) substrates using same 50 cycles of ALD at 50° C. sample temperature. Thus, the experiment showed 50 cycle deposition on 2D structures and for bilayer oxides. The use of the 50 cycle deposition and the bilayer with rotation to enable coating of 3D structures has also been demonstrated.

[0025] After the ALD process, Ni gates were deposited on the oxide by thermal evaporation. The gates were 50 μm in diameter and 3 nm thick. As a control, Ni/Al.sub.2O.sub.3/Si.sub.0.7Ge.sub.0.3/Al metal-oxide-semiconductor capacitors (MOSCAPs) were also fabricated with a slightly different process due to different cleaning and contact requirements. Prior to ALD, each Si.sub.0.7Ge.sub.0.3 (001) sample was treated with a 30 s rinse by each of acetone, isopropyl alcohol, and DI water followed by N.sub.2 drying. Afterwards, the native oxide was removed by cyclic HF cleaning using a 2% HF solution and DI water at 25° C. for 1 min in each solution for 2.5 cycles. For each SiGe sample, 50 cycles of ALD deposition were followed by Ni gate deposition and 100-nm thick Al back contact deposition using DC sputtering. For all samples, the capacitance-voltage curves were measured in the frequency range of 2 kHz to 1 MHz at room temperature with an HP4284A LCR meter. Leakage current of current of the oxide was obtained in the range of −2V to 2V.

[0026] FIGS. 1A-1C are AFM images of Al.sub.2O.sub.3 grown on HOPG using 50 cycles of ALD at sample temperatures of 200° C., 100° C., and 50° C. Each ALD cycle for the samples of FIGS. 1A-1C consisted of 600 ms TMA pulse and 50 ms H.sub.2O pulse, with 500 ms Ar purge times between precursor pulses. The growth of Al.sub.2O.sub.3 exhibited strong dependence on sample temperature. As shown in FIGS. 1A and 1B, when the sample temperature was above 100° C., Al.sub.2O.sub.3 was only deposited on the step edges of the HOPG and not on the terraces, because dangling bonds for nucleation are only available on the step edges and not on the inert terraces. The thickness of the Al.sub.2O.sub.3 deposited on the step edges was about 5 nm which is consistent with the expected thickness for 50 cycles of ALD at the typical 0.1 nm/cycle ALD growth rate.

[0027] When the sample temperature was decreased to below 100° C. (50° C.) as shown in FIG. 1C, the Al.sub.2O.sub.3 film was deposited continuously on both the step edges and the terraces without pin hole formation. Spherical Al.sub.2O.sub.3 features were observed across the entire surfaces for the growth at 50° C. sample temperature. However, these features are only observed with a short purge time between two precursor pulses at 50° C. sample temperature. When the purge time was increased to 2 s with identical precursor ALD pulse times and sample temperature, the spherical Al.sub.2O.sub.3 features were not observed as shown in FIG. 1D. Short purge times can induce a chemical vapor deposition (CVD) growth component since excess unreacted physisorbed precursor molecules have insufficient time to desorb from both the substrate and chamber walls during the short purge time. The CVD component induced deposition of particles of about 2±0.4 nm diameter which was quantified by averaging 10 AFM line scans. Al.sub.2O.sub.3 particles on the surface were formed by either nucleation in the ALD chamber and subsequently transported to the sample surface or were formed by precursor islands on the surface. Since surface island growth is usually non-spherical and similar nuclei were also observed on the MoS.sub.2 and reactive SiGe surface, the data is most consistent with nuclei formation in the ALD chamber.

[0028] The AFM images of FIGS. 2A-2C were taken after ALD was carried out using sequences of 600 ms TMA pulse and 50 ms H.sub.2O pulse with 500 ms of Ar purge after each precursor pulse. Spherical Al.sub.2O.sub.3 nuclei were observed on all three different substrates (white dots). This data is consistent with nuclei formation in the ALD chamber. The size of each image is 2×2 um.sup.2. The line profiles in FIGS. 2D-2F shows height profiles along the dotted lines, and provides information about the nuclei along the dotted lines.

[0029] Pulse Time Study

[0030] Samples were made with different pulse lengths of TMA and H.sub.2O with a fixed Ar purge time of 500 ms. For the sample with 200 ms TMA pulses and 50 ms H.sub.2O pulses Al.sub.2O.sub.3 was mainly deposited on the step edges. Although some Al.sub.2O.sub.3 was nucleated on the terraces, it was discontinuous with a high density of visible pinholes. The number densities of the Al.sub.2O.sub.3 particles (number of particles per 4 μm.sup.2 image area) with the three different ALD conditions are shown in Table I.

TABLE-US-00001 TABLE I Number density of Al.sub.2O.sub.3 particles from films grown with different ALD conditions (Number of particles per 4 μm.sup.2) 200 ms TMA & 600 ms TMA & 200 ms TMA & 50 ms H.sub.2O pulses 50 ms H.sub.2O pulses 150 ms H.sub.2O pulses 59 692 176

[0031] For a sample grown using relatively short 200 ms TMA pulses, the density of the Al.sub.2O.sub.3 particles (15 μm.sup.2) was significantly lower than for samples grown under different conditions with longer TMA pulse times. When the TMA pulse time was increased to 600 ms while fixing the H.sub.2O pulse length, the density of the Al.sub.2O.sub.3 particles was markedly increased (123 μm.sup.2) and continuous Al.sub.2O.sub.3 films were deposited on both terraces and step edges without pinholes. AFM line traces show that the particles are 2±0.6 nm in diameter. The observation of the high density of defects and low density of Al.sub.2O.sub.3 particles in the dielectric deposited using short TMA pulses indicates that the Al.sub.2O.sub.3 particles play a critical role in the formation of uniform dielectric layers on HOPG during ALD.

[0032] When the H.sub.2O pulse time was increased to 150 ms with a fixed TMA pulse time of 200 ms, similar morphology as for the growth with a long TMA pulse was observed. The Al.sub.2O.sub.3 film was continuous with a high density of Al.sub.2O.sub.3 particles (44/μm2) Data showed that the particles increased in size to 4±0.7 nm. This indicates that the Al.sub.2O.sub.3 particles were formed by a CVD component that can be controlled by the TMA and H.sub.2O pulse times. This observation is consistent with both the island formation mechanism and the gas phase formation mechanism for the particles.

[0033] Electrical Properties.

[0034] MIM capacitors were fabricated on freshly cleaved HOPG and MoS.sub.2 substrates. Al.sub.2O.sub.3 films were deposited using 50 ALD cycles consisting of 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge at 50° C. sample temperature. Subsequently, Ni metal gates were deposited by thermal evaporation. The area of the capacitor was ˜1900 μm.sup.2 (50 μm diameter). Capacitance-voltage (C-V) and leakage current-voltage (I-V) measurements were performed in order to evaluate the electrical quality of the oxide.

[0035] FIGS. 3A-3C are a comparison of Electrical Properties of Low Temperature Al.sub.2O.sub.3 ALD on HOPG and Si.sub.0.7Ge.sub.0.3 (001) with cycles consisting of a 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge at 50° C. sample temperature. FIG. 3A is a Capacitance vs. Voltage Curves of Ni/Al.sub.2O.sub.3 (50 ALD cycles)/HOPG stack at difference frequencies. FIG. 3B are Capacitance vs. Voltage Curves of Ni/Al.sub.2O.sub.3 (50 ALD cycles)/Si.sub.0.7Ge.sub.0.3/Al stack at different frequencies. FIG. 3C are I-V curves of Ni/Al.sub.2O.sub.3 (50 ALD cycles)/HOPG and Ni/Al.sub.2O.sub.3 (50 ALD cycles)/Si.sub.0.7Ge.sub.0.3/Al stack. The similar Cox on HOGP and Si.sub.0.7Ge.sub.0.3 (001) is consistent with no ALD induction cycles on HOPG. The comparable leakage currents of Al.sub.2O.sub.3/HOPG to Al.sub.2O.sub.3/Si.sub.0.7Ge.sub.0.3 are consistent with the oxide on HOPG being uniform and pin-hole free on the HOPG substrate.

[0036] As shown in FIG. 3A, the capacitance of the oxide was nearly independent of the applied voltage owing to the MIM structure of the capacitor. For single layer graphene, capacitance can be modulated near 0 V due to the linear dispersion of the density of states near the Fermi energy level. However, because of the high charge carrier density of HOPG near the Fermi energy level, the modulation of capacitance was not observed. The Cmax of the oxide was 1.17 μF/cm.sup.2 which is consistent with the Cmax value of the ALD grown Al.sub.2O.sub.3 on Si.sub.0.7Ge.sub.0.3 (001) as shown in FIG. 3B. This indicates that deposition of Al.sub.2O.sub.3 on HOPG proceeded without an ALD induction time. Note the high dispersion of the C-V data on Si.sub.0.7Ge.sub.0.3 was likely due to the formation of GeOx which can be suppressed by (NH.sub.4).sub.2S(aq) or NH.sub.3 plasma treatments and/or diminished with forming gas anneal. FIG. 3C compares the leakage currents of Al.sub.2O.sub.3 films grown by 50 ALD cycles on HOPG and Si.sub.0.7Ge.sub.0.3 (001) substrates. ALD was performed simultaneously at 50° C. sample temperature on the two substrates. The leakage current of the oxide on the HOPG was 3.1×10.sup.−5 A/cm.sup.2 and 2.2×10.sup.−6 A/cm.sub.2 for the Si.sub.0.7Ge.sub.0.3 at −1 V. The low leakage on Si.sub.0.7Ge.sub.0.3 is expected since Al.sub.2O.sub.3 readily nucleates on Si.sub.0.7Ge.sub.0.3 (001), and the Si.sub.0.7Ge.sub.0.3 (001) surface is flat without bunched steps. Conversely, HOPG surfaces are inert and have bunched steps. The leakage current of the ALD grown Al.sub.2O.sub.3 on HOPG at 50° C. sample temperature being within 15× of the leakage current on Si.sub.0.7Ge.sub.0.3 (001) is consistent with the oxide on HOPG being uniform and pin-hole free on the HOPG substrate

[0037] Additional experiments showed that an Al.sub.2O.sub.3 layer prepared by this ALD technique can be used as a good seeding layer for higher dielectric gate oxide such as HfO.sub.2. By making a bilayer stack consisting of bottom Al.sub.2O.sub.3—HfO.sub.2, higher Cox and lower EOT can be achieved. This was confirmed by examining electrical properties of MOSCAPs of MoS.sub.2, HOPG and Si.sub.0.7Ge.sub.0.3 (001) substrates with the bilayer gate oxide stacks. An identical preparation method was used for all substrates. 10 cycles of Al.sub.2O.sub.3 films were deposited using 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge at 50° C. sample temperature. HfO.sub.2 was deposited by consecutive cycles of 500 ms of TDMAH and 500 ms of H.sub.2O at 250° C. with 6 s long Ar purges after each precursor dose. Identical Ni metal gates were deposited by thermal evaporation. Insulating oxide was successfully deposited on three different samples. Cmax value was almost increased by factor of 2, compared to the samples on which 50 cycles of Al.sub.2O.sub.3 was deposited. The identical Cmax value among different substrates indicates that the oxide has same good quality on different surfaces. Comparable leakage currents of HfO.sub.2/Al.sub.2O.sub.3/HOPG and HfO.sub.2/Al.sub.2O.sub.3/MoS.sub.2 to HfO.sub.2/Al.sub.2O.sub.3/Si.sub.0.7Ge.sub.0.3 are consistent with the oxide on HOPG being uniform and pin-hole free on the HOPG and MoS.sub.2 substrates.

[0038] This technique can be also employed to 3D structure materials such as MoS.sub.2 Nanotubes. However, when using cross-flow type ALD, samples should be rotated during ALD process in order to obtain conformal deposition on the entire structures. Otherwise, non-uniform oxide could be produced due to the directional deposition along the gas flow in the chamber. MoS.sub.2 nanotubes were transferred by the edge of a dicing tape (Purchased from Semiconductor Equip. Corp, part number: 18074-9.00) on 27 nm of Al.sub.2O.sub.3 deposited by ALD onto a Si wafer. To remove possible polymer residues on the nanotube surface, the sample was transferred to a commercial UHV (Ultra High Vacuum) chamber under pressure of 10.sup.−10 torr and then annealed at 300 C for 10 min. After the UHV cleaning, 50 cycles of Al.sub.2O.sub.3 ALD with 600 ms of TMA pulse, 500 ms of Ar purge, 50 ms of H.sub.2O pulse and 500 ms of Ar purge was performed at 50° C. To avoid non-uniform deposition problem mentioned above, sample was rotated by 90 degrees after every 12 cycles. The Al.sub.2O.sub.3 deposited in this manner resulted in 5 nm thick uniform layer on the structure. HfO.sub.2—Al.sub.2O.sub.3Bilayer gate oxide stack was also employed to obtain higher Cox. 10 cycles of Al.sub.2O.sub.3 ALD with the identical recipe above was performed at 50° C. to provide a seeding layer for HfO.sub.2 ALD. 40 cycles of HfO.sub.2 was deposited on top of Al.sub.2O.sub.3 by 500 ms of TDMAH and 500 ms of H.sub.2O pulse with 6 s Ar purges after each precursor dose at 250° C. The oxide showed same uniform deposition on the MoS.sub.2 nanotube surface with 5 nm thickness.

[0039] The invention can also be applied to form devices such as FETs (Field Effect transistors), tunnel devices, display materials, memory devices (flash, DRAM etc), solar cells and etc. An example is selector devices for Resistive RAM or Flash or any cross-point memory. Ultrathin uniform conductive oxides such as indium tin oxide (ITO) can also be deposited on inert metals for memory applications, display materials or solar cells; ultrathin uniform conductive oxides can be deposited on 2D materials for displays or when the 2D materials is used in logic as a channel or diffusion barrier layers. In the devices, oxide layers are sometimes deposited on noble metal surfaces such as Pt, Au, and the oxide layers usually result in defective and non-uniform oxides with unacceptably high leakage current. The low temperature ALD can be used to initiate nucleation on such noble or inert metal surfaces. Using the technique, conformal and insulating Al.sub.2O.sub.3 was successfully prepared on Au gate electrodes.

[0040] FIG. 4 shows a cross-sectional schematic diagram of a dual bottom gated Field Effect Transistor 20 to which the present ALD method was employed to form nanolaminate gate oxides (the device structure and diagram are from the lab of Prof Zhihong Chen of Purdue, and the structure was used to test dielectrics of the present invention). The device was formed on a Si substrate 22 topped with an SiO.sub.2 dielectric layer 24. Two gate electrodes (TG1 and TG2) were isolated via nanolamiate oxides. A 1 nm thick Ti gate electrode was deposited on SiO.sub.2 on the Si substrate by e-beam evaporation and then 9 nm Au was deposited on top of the electrode. Prior to ALD, the sample was cleaned by rinsing with Acetone, IPA and H.sub.2O, respectively. 10 cycles of Al.sub.2O.sub.3 ALD with 600 ms TMA pulse, 500 ms Ar purge, 50 ms H.sub.2O pulse, and 500 ms Ar purge was performed at 50° C. to provide a seeding layer. 40 cycles of HfO.sub.2 ALD was deposited on top of Al.sub.2O.sub.3 by 500 ms of TDMAH and 500 ms of H.sub.2O pulse with 6 s Ar purges after each precursor dose at 250° C. The bilayer oxide prepared by this technique was insulting and the leakage current of the oxide was as low as 10.sup.−9 μA/μm.sup.2. TG2 consisted of him Ti (bottom) and 9 nm of Au (top). A device dielectric layer 26 was deposited by 10 cycles of Al.sub.2O.sub.3 ALD at 50° C. and 40 cycles of HfO.sub.2 ALD at 250° C. S(Source), D (Drain) were prepared by e-beam evaporation.

[0041] Experiments investigated a combined sequential low temperature (<100° C.) and high temperature (>200° C.) ALD oxide formation. 7 cycles of Al.sub.2O.sub.3 layer were deposited at 50° C. as a seeding layer. Afterwards, ALD reactor temperature was increased to 300° C. and 40 cycle of HfO.sub.2 ALD was deposited with HfCl.sub.4 and H.sub.2O on top of Al.sub.2O.sub.3. For comparison, identical oxides were deposited on MOS.sub.2, HOPG and Si.sub.0.7Ge.sub.0.3 (001). The same MOS CAP fabrication process was employed that was used for the pure Al.sub.2O.sub.3 MOSCAPs. However, the Cmax value was increased by factor of 2 (˜2 μF/cm.sup.2), compared to that of 50 cycles of Al.sub.2O.sub.3 due to the higher dielectric constant of HfO.sub.2. The identical Cmax value for the different substrates is consistent with identical growth rates and no inductions period during the ALD. Comparable leakage currents among the three samples indicated the oxides are insulating and uniform on both 2D materials and Si.sub.0.7Ge.sub.0.3 (001) substrate.

[0042] The effect of the oxygen scavenging by Ti/TiN metal gate on a gate oxide was also investigated. Pd/Ti/TiN top gates were fabricated on the HfO.sub.2/Al.sub.2O.sub.3 bilayer oxide (10 cycle of Al.sub.2O.sub.3 at 50° C. (interface)/40 cycle of HfO.sub.2 at 300° C.) by DC sputtering. Identical oxides and gates were deposited on MoS.sub.2, HOPG and Si.sub.0.7Ge.sub.0.3 (001) and the MOSCAP fabrication process was identical to the bilayer MOSCAP with nonreactive gates. FIGS. 5A-5C present the capacitance-voltage measurements. The Cmax of the three MOSCAPs was increased to ˜2.7 μF/cm.sup.2 which was about 30% higher compared to a HfO.sub.2/Al.sub.2O.sub.3 bilayer stack with Ni Gate. This improvement suggests that Pd/Ti/TiN gate scavenge oxygen from the gate oxide resulting in an increase of dielectric constant of the layer or thinner interface oxide layer (for SiGe). The Cmax of Si.sub.0.7Ge.sub.0.3 (001) MOSCAPs was higher (˜3.0 μF/cm.sup.2) compared to MoS.sub.2, HOPG. This fact indicates that the scavenging oxygen is more effective on Si.sub.0.7Ge.sub.0.3 (001) than MoS.sub.2 and HOPG since there is an SiGeOx interlayer. FIGS. 5D-5F show the leakage current measurement of three MOSCAPS. Leakage current density showed that lower EOT was achieved without increase of leakage current.

[0043] As shown in FIGS. 6A and 6B, with optimized pulse and purge times the vast majority of the Al.sub.2O.sub.3 nuclei can be reduced in size below the resolution of the AFM which is about 1 nm. There a few large nuclei (<1%) which are dust from the ALD reactor. The nanofog films in FIGS. 6A-6B were produced via 50 cycles of Al.sub.2O.sub.3 films on bulk MoS.sub.2 with different purge times. The FIG. 6A nanfog film 50 ALD cycle consisted of a 600 ms TMA pulse, a 500 ms Ar purge, a 50 ms H.sub.2O pulse, and a 3 s Ar purge. The FIG. 6B nanofog film 50 ALD cycle consisted of a 600 ms TMA pulse, a 500 ms Ar purge, a 50 ms H.sub.2O pulse, and a 3 s Ar purge at 50° C. The size of the images is 2×2 um.sup.2. The nanofog films consist essential of sub-1 nm particle and provide a platform for further ALD depositions.

[0044] While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

[0045] Various features of the invention are set forth in the appended claims.