In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 μm at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of metal same with a metal contained in the lower layer of the lower electrode.

A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.

An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 μm in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×10.sup.21/cm.sup.3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH.sub.4HF.sub.2) of 7.13% and an ammonium fluoride (NH.sub.4F) of 15.4%.

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

The present disclosure relates to a method of manufacturing a thin film device. A multilevel nanoimprint lithography template is transferred into a thin film stack comprising an electrode layer and a blanket sacrificial layer covering the electrode layer. The template is transferred, thereby patterning the device and exposing a predefined insulating area of the electrode while keeping a remaining portion of the sacrificial layer that covers a pre-defined electrical contact area of the electrode. An area selective atomic layer deposition (ALD) process is performed to selectively cover the exposed area of the electrode layer with a cover layer. After removing the remaining portion of the sacrificial layer the electrical contact area of the electrode layer is exposed for further processing.

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

The present invention belongs to the field of display technology and provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate, a source, a drain and a plurality of insulating layers, wherein at least one insulating layer comprises a Group VB metal oxide. Since the insulting layer is formed by using the Group VB metal oxide which has high dielectric constant, the thickness of the insulating layer can be reduced and the thin film transistor can be miniaturized.

A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.