The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.

Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (V.sub.t) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.

A display apparatus includes an oxide semiconductor pattern disposed on a device substrate and including a channel region disposed between a source region and a drain region, a gate electrode overlapping the channel region of the oxide semiconductor pattern and having a structure in which a first hydrogen barrier layer and a gate conductive layer are stacked, and a gate insulating film disposed between the oxide semiconductor pattern and the gate electrode to expose the source region and the drain region of the oxide semiconductor pattern. The gate electrode exposes a portion of the gate insulating film that is adjacent to the source region and a portion of the gate insulating film that is adjacent to the drain region.

A method includes providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another; forming an interfacial layer wrapping around each of the semiconductor layers; forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers; and forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers. With the capping layer wrapping around each of the semiconductor layers, the method further includes performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer. After the performing of the thermal treatment, the method further includes removing the capping layer.