Patent classifications
H01L29/495
Temperature compensation circuits
The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.
System and method of manufacturing a thin film transistor substrate
In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed.
Formation of work-function layers for gate electrode using a gas cluster ion beam
An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.
Memory structure and manufacturing method of the same
A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.
Gate-all-around field effect transistor having multiple threshold voltages
One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
Transistor device and fabrication method
The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance.
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
Spatial terahertz wave phase modulator based on high electron mobility transistor
A spatial terahertz wave phase modulator based on the high electron mobility transistor is provided. The phase modulator combines the quick-response high electron mobility transistor with a novel metamaterial resonant structure, so as to rapidly modulate terahertz wave phases in a free space. The phase modulator includes a semiconductor substrate, an HEMT epitaxial layer, a periodical metamaterial resonant structure and a muff-coupling circuit. A concentration of 2-dimensional electron gas in the HEMT epitaxial layer is controlled through loading voltage signals, so as to change an electromagnetic resonation mode of the metamaterial resonant structure, thereby achieving phase modulation of terahertz waves. The phase modulator has a phase modulation depth of over 90 degrees within a large bandwidth, and a maximum phase modulation depth is about 140 degrees. Furthermore, the phase modulator is simple in structure, easy to machine, high in modulation speed, convenient to use, and easy to package.
Fabrication of IGZO oxide TFT on high CTE, low retardation polymer films for LDC-TFT applications
The present invention provides a TFT on a polymer substrate and a method for producing the TFT. The TFT is, due to its characteristics, particularly suited for applications as backplane in LCD displays and solar cell devices.
Controlling current or mitigating electromagnetic or radiation interference effects using multiple and different semi-conductive channel regions generating structures
Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using multiple different semi-conductive channel regions generating structures formed by multiple different semi-conductive electrical current or voltage control structures. One embodiment includes providing a first and second metal oxide semiconductor field effect transistor (MOSFET) sections formed on opposite sides of a metal-semiconductor field effect transistor (MESFET) such that operation of the MESFET modulates or controls current otherwise controlled by an electrical path of the MOSFET sections. A control system for determining when an embodiment of the invention is to be operated is also provided to include automated systems including sensors as well as manually operated systems. Automated systems can include radiation sensors as well as other control systems such as high voltage radio frequency transmitter or receiver systems. Methods of operation for a variety of modes are also provided.