Fabrication of IGZO oxide TFT on high CTE, low retardation polymer films for LDC-TFT applications

Abstract

The present invention provides a TFT on a polymer substrate and a method for producing the TFT. The TFT is, due to its characteristics, particularly suited for applications as backplane in LCD displays and solar cell devices.

Claims

1. A thin film transistor on a polymer substrate, comprising: a gate electrode; a gate insulating film covered by the gate electrode, the gate insulating film comprising methylsiloxane having a methyl content in the range of from ≧1 wt.-% to ≦13 wt.-%; a semiconductor channel layer placed to face the gate electrode with the gate insulating film interposed there between, the semiconductor channel layer comprising at least one of a metal oxide semiconductor including an oxide of at least one of Hf, In, Ga, or Zn and mixtures thereof; a source drain pattern comprising a source electrode connected to the semiconductor layer and a drain electrode separated from the source electrode and connected to the semiconductor layer, wherein the semiconductor layer has a source portion that contacts the source electrode, a drain portion that contacts the drain electrode, and a channel portion that is located between the source and drain portions; wherein the gate electrode and the source and gate electrodes comprise at least one of Al, Ti, Mo, AlNd, a stack metal electrode Ti/Al/Ti, or a transparent conducting oxide selected from the group consisting of indium tin oxide, indium doped zinc oxide, aluminum doped zinc oxide, fluorine tin oxide, antimony tin oxide, and mixtures thereof; a polymer substrate comprising a thermoplastic polymer film.

2. The thin film transistor according to claim 1, wherein polymer substrate further comprises a planarized hard coat layer on at least one side of the thermoplastic polymer film, and wherein the planarized hard coat layer comprises a UV cured acrylate or a thermally cured planarizier.

3. The thin film transistor according to claim 1, wherein the thermoplastic polymer film of polymer substrate comprises polycarbonates, polyethylene terephthalate, polyurethane, polyetherketones, polyethylene, polystyrene, polyvinylalcohole, epoxide resins or polyamides, wherein the thermoplastic polymer film has a T.sub.g of at least 160° C.

4. The thin film transistor according to claim 2, wherein the hard coat of the polymer substrate comprises ionization curing polyester acrylate and/or urethane acrylate.

5. The thin film transistor according to claim 1, wherein the thermoplastic polymer film of polymer substrate comprises polycarbonate, wherein said polycarbonate is a high molecular weight, thermoplastic, aromatic polycarbonate with M.sub.w (weight average of the molecular weight) of at least 10 000, which comprise bifunctional carbonate structural units of formula (I), ##STR00005## wherein R.sup.1 and R.sup.2 independently of one another are hydrogen or halogen, m is an integer of from 4 to 7, R.sup.3 and R.sup.4 is selected for each X individually and, independently of one another, is hydrogen or C.sub.1-C.sub.6 alkyl and X is carbon, and n is an integer of 30 or greater, with the proviso that, on at least one X atom, R.sup.3 and R.sup.4 simultaneously are alkyl.

6. The thin film transistor according to claim 5, wherein the polycarbonate is a copolycarbonate having structural units of formula (I-h) ##STR00006## wherein the comonomers can be in an alternating, block or random arrangement in the copolymer, p+q=n and the ratio of q is such that the diphenols containing the spirocompound are contained in quantities of from 100 mole % to 2 mole %, based on the total quantity of 100 mole % of diphenol units, in polycarbonates.

7. The thin film transistor according to claim 2, wherein the thermoplastic polymer film has a thickness in the range of from ≧50 μm to ≦350 μm and the hard coat has a thickness in the range of from ≧3 μm to ≦15 μm.

8. A method utilizing the thin film transistor according to claim 1 as TFT backplane for active matrix displays.

9. A method for producing a thin film transistor on a polymer substrate, the method comprising the steps of: (a) laminating a polymer substrate comprising a thermoplastic polymer film onto a glass carrier; (b) depositing a layer of aluminum oxide on the polymer substrate, thereby forming a barrier and adhesion layer; (c) depositing gate electrode layer, the step comprising depositing a metal and/or metal oxide film and a subsequent photolithographic treatment; (d) coating with methylsiloxane having a methyl content in the range of from ≧1 wt.-% to ≦13 wt.-%, and subsequent annealing at a lower temperature than T.sub.G of the polymer substrate, thereby forming the gate insulating film; (e) depositing a metal and/or metal oxide film and carrying out a photolithographic treatment to form source drain pattern; (f) depositing an oxide layer comprising at least one oxide of Hf, In, Ga or Zn to form semiconductor layer, wherein the metal or metal oxide of (c) and (e) comprise at least one of Al, Ti, Mo, AlNd, a stack metal electrode Ti/Al/Ti, or a transparent conducting oxide selected from the group consisting of indium tin oxide, indium doped zinc oxide, aluminum doped zinc oxide, fluorine tin oxide, antimony tin oxide, and mixtures thereof.

10. The method according to claim 9, wherein the thermoplastic polymer film of polymer substrate comprises polycarbonates, polyethylene terephthalate, polyurethane, polyetherketones, polyethylene, polystyrene, polyvinylalcohole, epoxide resins or polyamides, wherein the thermoplastic film has a T.sub.g of at least 160° C.

11. The method according to claim 9, wherein the thermoplastic polymer film of polymer substrate comprises polycarbonate, wherein said polycarbonate is a high molecular weight, thermoplastic, aromatic polycarbonate with M.sub.w (weight average of the molecular weight) of at least 10 000, which contain bifunctional carbonate structural units of formula (I), ##STR00007## wherein R.sup.1 and R.sup.2 independently of one another are hydrogen or halogen, m is an integer of from 4 to 7, R.sup.3 and R.sup.4 may be selected for each X individually and, independently of one another, and are hydrogen or C.sub.1-C.sub.6 alkyl and X is carbon, and n is an integer of 30 or greater, with the proviso that, on at least one X atom, R.sup.3 and R.sup.4 simultaneously are alkyl.

12. The method according to claim 9, wherein the annealing in step d) is carried out over a time in the range of from ≧0.5 h to ≦10 h.

13. The method according to claim 9, wherein the polymer substrate further comprises a planarized hard coat layer on at least one side of the thermoplastic polymer film, and wherein the planarized hard coat layer comprises a UV cured acrylate or a thermally cured planarizier.

14. The method according to claim 9, wherein the methylsiloxane in step d) has a methyl content in the range of from ≧6 wt.-% to ≦11.5 wt.-%.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 shows the shrinkage in MD for a 72 h annealed polycarbonate substrate used in the present invention (Makrofol® HS 279). On the x-axis is the shrinkage in MD=0.010% in a thermal shrinkage test (150° C., 30 min). On the y-axis is the shrinkage in TD=0.000% in a thermal shrinkage test (150° C., 30 min).

(2) FIG. 2 shows a metal gate array.

(3) FIG. 3 depicts the cross section of the thin film transistor up to the gate insulator. In particular, on top of the bottom polymer substrate layer (100) is the barrier and adhesion layer (150), the gate electrode (200) and the gate insulator (300).

(4) FIG. 4 shows essentially the same parts as FIG. 5 except for the film (400) on the gate insulator layer (300).

(5) FIG. 5 depicts the finished source drain pattern (450) after the photolithographic treatment of layer (400).

(6) FIG. 6 finally shows the crosslink of a finished TFT, comprising the polymer substrate (100), barrier and adhesion layer (150), the gate electrode (200), gate insulator (300), source drain pattern (450) and IGZO channel island (500).

(7) FIG. 7 shows the final DUV treatment of the TFI.

(8) FIG. 8 depicts the transfer characteristics of said TFT which has been annealed for 2 h at 150° C. in an nitrogen atmosphere. The TFT showed a field effect mobility of approximately 35 cm.sup.2/Vs and On/Off ratio of approximately 0.5.Math.10.sup.6.

(9) FIG. 9 shows a single IGZO oxide TFT on a polycarbonate substrate comprising source, drain, gate and a channel according to the present invention.

(10) FIG. 10 shows the centrosymmetric alignment according to an embodiment of the present invention. The centrosymmetric alignment comprises using three alignment marks, equidistant from each other, at the apex of an equilateral triangle. This alignment method optimizes the alignment of the source and drain electrode in the gate of the transistors over the array. The alignment mark for the gate is the cross and the alignment mark for source and drain consists of four squares.

EXAMPLES

Example 1

(11) APEC Polycarbonate (80 μm) coated both sides with a 4 μm high cross linked UV acrylate planarizer (Makrofol® HS279, layer 100, Bayer Material Science AG) sheets were heat treated in Dry Oven (Binder FDL 115) at 180° C. for 72 hours. The film turned slightly yellow. However, pre-annealing in a vacuum oven prevented photo-oxidation and yellowing, and was transparent after 72 hours annealing in vacuum to remove water in the polycarbonate film. Samples of dimensions 35 cm×35 cm were cut.

Example 2

(12) The samples (bottom planarizer coating) obtained in example 1 were laminated onto a glass carrier using a manual roller at room temperature with an Intelimer Tape from Nitta Corporation, (CS2325NA3). For even better lamination, the lamination may be done at 150° C. with an Obducat soft press technology up to 6 MPA (60 bars) so as to achieve a highly optically flat film laminated firmly onto the glass carrier). The samples were then cleaned by sonication in isopropyl alcohol (IPA).

Example 3

(13) An 18 nm coating of aluminum oxide (layer 150) was deposited on top of the planarizer coating of the samples obtained in example 3 by Atomic layer deposition at 150° C. (Savannah 100 from Cambridge Nanotech Inc.) as a water vapour and oxygen barrier as well as an adhesion layer for the aluminum gate.

Example 4

(14) A 200 nm aluminum film was deposited by E-beam evaporation (Edwards Auto 306) on the film obtained in example 3. A hexamethyldisoloxane (HMDS) monolayer film was deposited by HMDS oven (Yield engineering) to promote adhesion to photoresist. A Z1505 photoresist was spun at a speed of 4000 rpm for 60 seconds to yield a film having a thickness of about 0.6 μm. The photoresist film was then baked at 95° C. for 60 seconds. The film was then exposed using a Karl Suss MA8 contact aligner system and a quartz chrome lithographic mask with the gate pattern for an array of 210 TFTs as in FIG. 2. The exposed film was then developed for 20 seconds in AZ developer diluted with water in the ratio 1:1. Then the sample was dipped in Transene Aluminium etchant at 50° C. for 75 seconds to etch the aluminum not covered by the photoresist. The photoresist was then subsequently stripped in a reactive ion etching (RIE) system (Oxford plasma) using oxygen as the etching gas for 8 minutes. The use of the relatively thinner photoresist film made it easier to strip it away by a dry etching process (O.sub.2 RIE) instead of using a wet chemical stripper which would have damaged the substrate. Alignment marks were made on the substrate for aligning with the subsequent layers like source/drain and channel island. The gate array is shown in FIG. 2.

Example 5

(15) T-314 Spin-On Glass from Honeywell electronic materials was spun at 1000 rpm for 60 s. The spin coated samples were then baked on hot plate inside a nitrogen filled glove box at 120° C. for 2 min and subsequently at 150° C. The misalignment of the source and drain electrode to the gate electrode could be reduced with longer heating time. A 3 hour annealed sample was found to have better alignment than a 2 hour annealed sample. Thermal heating was capped at 150° C. so as to not exceed the T.sub.g of HS 279 at 170° C. A thickness of 340 nm was obtained for the methyl siloxane layer (300). FIG. 3 shows a cross section of the structure.

Example 6

(16) An aluminum film of 200 nm was deposited onto the gate insulator (layer 400) as shown in FIG. 4). Then HMDS and photoresist film was deposited as described earlier. The three alignment marks on the source drain pattern on the quartz chrome mask were aligned to the three alignment marks on the HS 279 device wafer in a centro-symmetric manner to optimize the alignment of source and drain electrode to the gate electrode. The photoresist film was exposed and developed. Etching the aluminum and stripping of the photoresist was also done as described earlier to yield the source drain pattern (layer 450) which is shown in FIG. 5.

Example 7

(17) Another layer of HMDS and a thicker AZ5214E photoresist film were spin coated. The gate pattern was aligned to the channel semiconductor pattern on a quartz chrome mask by using the MA8 aligner. Then the film was exposed using an image reversal process and developed using AZ400K developer. A 35 nm IGZO layer (layer 500) was deposited by RF sputtering (Nanofilm) using Ar:N.sub.2 as sputtering gas. The sample was then subjected to a pro-lift off cleaning step using wafer clean 2100 (Eco-snow systems) which utilises dry CO.sub.2. The substrate was then dipped in acetone for 25 minutes to lift off followed by sonication in acetone for 5 minutes to yield a clean IGZO oxide TFT as in FIG. 6. There was an only slight damage to the edge of the substrate observed, which was probably caused by acetone.

Example 8

(18) Another layer of HMDS and AZ 1505 photoresist film was deposited as described earlier. The gate pattern was aligned to a pattern to open via contact to gate on a quartz chrome mask by using the MA8 aligner and then the film was exposed and developed. 15 minutes etching of the methyl siloxane gate insulator layer on top of the gate bond pads was carried out in a RIE system using Ar—CHF.sub.3 etching gas mixture and the photoresist was stripped as described earlier in example 5.

Example 9

(19) A sample obtained in example 8 was then annealed in a glove box at 150° C. for 3 hours. This was followed by a further deep ultra violet (DUV) (184 nm to 265 nm) annealing of the transistor in a nitrogen environment, (see FIG. 7). The DUV was readily absorbed by the IGZO semiconductor (band gap of ˜3.3 eV, with corresponding wavelength λ˜375.7 nm), which in turn annealed the IGZO semiconductor as well as the methyl siloxane gate dielectric in the area of the channel. An example of a transistor annealed at 150° C. for 2 hours in nitrogen showed a field effect mobility of ˜35 cm.sup.2/Vs and On/Off ratio of ˜0.5×10.sup.6 (transfer characteristics are shown in FIG. 8).