A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

A method includes following steps. Fins are formed over a substrate. A dummy gate structure is across the fins. A spacer layer is deposited over the dummy gate structure. The spacer layer has a first portion in a void of the dummy gate structure and a second portion outside the void of the dummy gate structure. The second portion of the spacer layer is treated to have a different material composition than the first portion of the spacer layer, and is then etched to form gate spacers on sidewalls of the dummy gate structure. An etching process is performed on the dummy gate structure to form a gate trench between the gate spacers. The etching process etches the first portion of the spacer layer at a faster etch rate than etching the gate spacers. A gate structure is formed in the gate trench.

A semiconductor device includes a substrate, a gate oxide layer, a gate electrode and an injection region. The substrate includes a trench, a source region, a drain region and a channel region. The trench includes trench sidewalls and a trench bottom wall. The gate oxide layer is disposed in the trench. The gate oxide layer includes a groove. The gate electrode is disposed in the groove. The injection region is located on at least a side of the trench bottom wall, and at least a part of the injection region is closer to the drain region than the source region so that a threshold voltage at a portion of the channel region close to the injection region is less than a threshold voltage at a portion of the channel region far from the injection region.

A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first region, and a first transistor positioned in the first region. The first transistor includes a first bottom gate structure positioned on the substrate, a first channel layer positioned on the first bottom gate structure, a first top gate structure positioned on the first channel layer, and two first source/drain regions positioned on two sides of the first channel layer.

A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.

Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.

Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.