H01L29/6606

SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME
20220157606 · 2022-05-19 ·

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20220149174 · 2022-05-12 · ·

A semiconductor device includes: a semiconductor substrate; a semiconductor layer of a first conductivity type that is deposited on a surface of the semiconductor substrate; a trench that is formed on a surface of the semiconductor layer; an insulating film that covers a bottom surface of the trench and a lateral surface of the trench; a conductive body that fills inside the trench that is covered by the insulating film; a second conductive type region that is formed in the semiconductor layer, is arranged under the trench, and is within a region of the trench in a plan view of the semiconductor substrate; and a metal film that is electrically connected to the conductive body and forms a Schottky barrier with the surface of the semiconductor layer.

SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE EPITAXIAL SUBSTRATE
20230261057 · 2023-08-17 ·

A silicon carbide epitaxial substrate according to the present disclosure includes: a silicon carbide substrate; a first silicon carbide epitaxial layer disposed on the silicon carbide substrate; and a second silicon carbide epitaxial layer disposed on the first silicon carbide epitaxial layer. When an area density of first particles in the first silicon carbide epitaxial layer is defined as a first area density and an area density of second particles in the second silicon carbide epitaxial layer is defined as a second area density, a value determined by dividing the first area density by the second area density is more than 0.5 and less than 1. The first particles and the second particles each have a maximum diameter of 2 μm to 50 μm.

WIDE-BAND GAP SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
20230261119 · 2023-08-17 · ·

A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.

Merged PiN Schottky (MPS) diode with plasma spreading layer and manufacturing method thereof
11728439 · 2023-08-15 ·

A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Semiconductor device including junction material in a trench and manufacturing method

An embodiment of a semiconductor device comprises a SiC semiconductor body, a gate dielectric and a gate electrode. A first trench extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. A junction material is in the first trench, wherein the junction material and the SiC semiconductor body form a diode.

SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a field insulating film formed on an epitaxial layer, a front surface electrode covering an inner peripheral end of the field insulating film, and an outer peripheral electrode covering an outer peripheral end of the field insulating film. In a surface layer portion of the epitaxial layer, a termination well region that is connected to the front surface electrode and extends to the outside of an outer peripheral end of the front surface electrode is formed. The semi-insulating film is formed so as to cover a part of the field insulating film apart from the front surface electrode and the outer peripheral electrode. The semi-insulating film is connected to the epitaxial layer through an opening formed in the field insulating film in each of a region inside and a region outside an outer peripheral end of the termination well region.

CHARGE BALANCED RECTIFIER WITH SHIELDING

SiC Schottky rectifiers are described with a Silicon Carbide (SiC) layer, a metal contact, and an n-type channel region disposed between the SiC layer and the metal contact. A p-pillar may be formed adjacent to the metal contact and extending in a direction of the SiC layer, and a a p-type shielding body adjacent to the metal contact and extending from the metal contact in a direction of the SiC layer. The SiC Schottky rectifiers may include a first channel region of the n-type channel region having a first n-type doping concentration, and disposed between the p-pillar and the p-type shielding body, the first channel region being adjacent to the metal contact. The SiC Schottky rectifiers may include an n-pillar providing a second channel region of the n-type channel region and having a second n-type doping concentration that is lower than the first n-type doping concentration in the first channel region, the n-pillar being disposed adjacent to the first channel region, and to the p-pillar.

Junction barrier schottky diode

A junction barrier schottky (JBS) diode is provided and includes: a bottom metal layer, a N.sup.+-type substrate layer and a N.sup.−-type epitaxial layer sequentially arranged in that order from bottom to top, P-type ion injection regions are disposed on an upper surface of the N.sup.−-type epitaxial layer, distances of the P-type ion injection regions are gradually increased along a direction from an edge to a center of the JBS diode; an isolation dielectric layer is arranged on a periphery of the upper surface of the N.sup.−-type epitaxial layer, an top metal layer is arranged on the upper surface of the N.sup.−-type epitaxial layer and an upper surface of the isolation dielectric layer and further is in contact with the P-type ion injection regions. The JBS diode can effectively inhibit an occurrence of local electromigration and improve a device reliability.

Junction barrier Schottky diode device and method for fabricating the same

A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.