A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

Methods for designing semiconductor components, for fabricating semiconductor components, and corresponding semiconductor components are provided. In this case, capacitance structures are either coupled to a supply network or used for rectifying design violations.

A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.

Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/−1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.

The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements.

Silicon carbide junction barrier Schottky diode disclosed. Silicon carbide junction barrier Schottky diode includes a first conductivity-type substrate, a first conductivity-type epitaxial layer, being formed by epitaxial growth of silicon carbide doped with a first conductivity-type impurity on the first conductivity-type substrate, a charge injection region, being formed on the first conductivity-type epitaxial layer and doped at a concentration of the first conductivity-type impurity higher than that of the first conductivity-type epitaxial layer, a second conductivity-type junction region, being formed on the first conductivity-type epitaxial layer so as to contact the charge injection region, a Schottky metal layer, being formed on the charge injection region and the second conductivity-type junction region, an anode electrode, being formed on the Schottky metal layer, and a cathode electrode, being formed under the first conductivity-type substrate.