Patent classifications
H01L29/66068
Silicon carbide components and methods for producing silicon carbide components
A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
RF SiC MOSFET WITH RECESSED GATE DIELECTRIC
A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.
POWER SEMICONDUCTOR DEVICE
A power semiconductor device includes a base semiconductor layer including impurities of a first conductivity type; a body portion provided on the base semiconductor layer and defined by a source trench, the body portion including a gate trench extending inwardly from an upper surface of the body portion; a gate electrode provided in the gate trench; a source electrode provided on the body portion and spaced apart from the gate electrode; and a drain electrode provided below the base semiconductor layer, wherein the body portion includes: a drift layer provided on the base semiconductor layer and including impurities of the first conductivity type; and a pair of shielding regions provided in the drift layer, spaced apart from each other in a horizontal direction, and spaced apart from the base semiconductor layer and the gate trench, the pair of shielding regions including impurities of a second conductivity type different from the first conductivity type.
Semiconductor device
According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.
Trenched power device with segmented trench and shielding
A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.
MOSFET WITH SATURATION CONTACT AND METHOD FOR FORMING A MOSFET WITH SATURATION CONTACT
A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.
SEMICONDUCTOR HIGH-VOLTAGE TERMINATION WITH DEEP TRENCH AND FLOATING FIELD RINGS
A semiconductor device comprises a substrate, a semiconductor layer formed on the substrate; and a high-voltage termination. The high-voltage termination includes a plurality of floating field rings, a deep trench and a dielectric material is disposed within the deep trench. The plurality of floating field rings are formed in the semiconductor layer and respectively disposed around a region of the semiconductor layer. The deep trench is formed in the semiconductor layer and concentrically disposed around an outermost floating field ring of the plurality of floating field rings. The high-voltage termination may also include a field plate disposed over the floating field rings, the deep trench, or both.
SEMICONDUCTOR DEVICE WITH DEEP TRENCH AND MANUFACTURING PROCESS THEREOF
A semiconductor device is formed having a deep trench, a conductive material disposed in the deep trench, and a dielectric disposed within the deep trench and separating the conductive material from surfaces of the deep trench. The conductive material may be carbon, and may be formed by pyrolysis of an organic material such as a photoresist. The deep trench and the conductive material may be parts of a high-voltage termination of an active device of the semiconductor device. The conductive material may be floating or may be connected to an electrode of the active device.
METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE
A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.
SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.