A semiconductor device having, in a plan view thereof, an active region and a termination region that surrounds a periphery of the active region. The device includes a semiconductor substrate containing a wide bandgap semiconductor, a first-conductivity-type region provided in the semiconductor substrate, spanning from the active region to the termination region, a plurality of second-conductivity-type regions provided between the first-conductivity-type region and the first main surface of the semiconductor substrate in the active region, a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the second-conductivity-type regions, a second electrode provided on the second main surface of the semiconductor substrate and electrically connected to the first-conductivity-type region, and a lifetime killer region provided in the first-conductivity-type region and spanning from the active region to the termination region. In the active region, pn junctions between the first-conductivity-type region and the second-conductivity-type regions form a vertical semiconductor device element.

An SBD of a JBS structure has on a front side of a semiconductor substrate, nickel silicide films in ohmic contact with p-type regions and a FLR, and a titanium film forming a Schottky junction with an n.sup.−-type drift region. A thickness of each of the nickel silicide films is in a range from 300 nm to 700 nm. The nickel silicide films each has a first portion protruding from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion protruding in the semiconductor substrate from the front surface of the semiconductor substrate in a depth direction. A thickness of the first portion is equal to a thickness of the second portion. A width of the second portion is wider than a width of the first portion.

An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.

On a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, an interlayer insulating film, first electrodes, and a second electrode are formed. Each of the first electrodes are formed by depositing a lower Ni film, an Al film, and an upper Ni film and etching the films to be apart from the interlayer insulating film; sintering the lower Ni film by a heat treatment and thereby forming a Ni silicide film; depositing a Ti film, a TiN film, and an AlSi film; and etching the AlSi film.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region. In a plan view in a direction normal to the first main surface, the gate trench and the electric field relaxation region are disposed on a virtual line that extends in the first direction, and the connection region is in contact with the electric field relaxation region on the virtual line.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.

A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate. The first-conductivity-type regions of the first and third partial parallel pn layers face each other in a depth direction of the silicon carbide substrate, and the second-conductivity-type regions partial parallel pn layers face each other in the depth direction.

To provide a technique capable of improving performance and reliability of a semiconductor device. An n.sup.−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p.sup.+-type body region (14), n.sup.+-type current spreading regions (16, 17), and a trench. TR are formed in the n.sup.−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p.sup.+-type body region (14), a side surface S1 of the trench TR is in contact with the n.sup.+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n.sup.+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n.sup.−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n.sup.−-type epitaxial layer (12) is inclined with respect to the side surface S2.

A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is in contact with each of the second impurity region and the third impurity region on the first main surface. The second electrode is in contact with the first impurity region on the second main surface. The second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region. An impurity concentration of the first region is more than or equal to 6×10.sup.16 cm.sup.−3.

In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.