A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes, a clamp circuit including an MOS transistor integrated with a silicon controlled rectifier (SCR) and a trigger circuit. In response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage. In other embodiments, a bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.

A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact to pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.

According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.

A semiconductor element includes a semiconductor part, first to third electrodes and a control electrode. The first electrode is provided at a front side of the semiconductor part. The second and third electrodes are provided at a back side of the semiconductor part. The control electrode is provided between the semiconductor part and the first electrode. The semiconductor part includes first and third layers of a first conductivity type and second and fourth layers of a second conductivity type. The first layer is provided between the first and second electrodes and between the first and third electrodes. The first layer is connected to the third electrode at the back side. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer is provided between the second electrode and the first layer.

A semiconductor device includes a semiconductor substrate, a first anode electrode, and a second anode electrode. The first anode electrode is disposed on the semiconductor substrate. The second anode electrode is spaced from the first anode electrode on the semiconductor substrate around the first anode electrode. At least any of a first end of the first anode electrode on a second anode electrode side and a second end of the second anode electrode on a first anode electrode side is covered with a SInSiN film.

Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n− buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n− buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n− buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.