An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

In a switching circuit, an inductance of an inductor of a shunt circuit is such that off capacitance of a second switching device that is in the off state when a first switching device is in the on state is used to define, in the shunt circuit, a series resonance circuit with a desired resonant frequency. Therefore, the frequency of an unnecessary signal to be attenuated is set to the resonant frequency of the series resonance circuit. Thus, the switching circuit achieves improved isolation characteristics with other circuits by attenuating the unnecessary signal.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Electronic devices are formed on donor substrates and transferred to carrier substrates by forming bonding regions on the electronic devices and bonding the bonding regions to a carrier substrate. The transfer process may include forming anchors and removing sacrificial regions.

An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.

An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.

A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.