The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.

A semiconductor device including a protected element, a contact region, wiring, and a channel stopper region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. The periphery of the diode is surrounded by an element isolation region. The contact region is arranged at a portion on a main face of the anode region, and is set with a same conductivity type as the anode region, and set with a higher impurity concentration than the anode region. The wiring is arranged over the diode. One end portion of the wiring is connected to the contact region and another end portion extends over a passivation film. The channel stopper region is arranged at a portion on the main face of the anode region under the wiring between the contact region and the element isolation region, and is set with an opposite conductivity type to the contact region.

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface and an active device region. First through fourth surface contact areas at the first main surface are arranged directly one after another along a lateral direction. The semiconductor body is electrically contacted at each surface contact area. First and third SCR regions of a first conductivity type directly adjoin the first and third surface contact areas, respectively. Second and fourth SCR regions of a second conductivity type directly adjoin the second and fourth surface contact areas, respectively. The second SCR region at least partially overlaps a first well region of the first conductivity type at the first main surface. The first SCR region at most partially overlaps the first well region at the first main surface, and is electrically connected to the second SCR region. The third SCR region is electrically connected to the fourth SCR region.

An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes, a clamp circuit including an MOS transistor integrated with a silicon controlled rectifier (SCR) and a trigger circuit. In response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage. In other embodiments, a bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes, a clamp circuit including an MOS transistor integrated with a silicon controlled rectifier (SCR) and a trigger circuit. In response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage. In other embodiments, a bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.