A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

Reliability of an electrical test of a semiconductor wafer is improved. A method of manufacturing a semiconductor device includes a step of performing an electrical test of a semiconductor element by allowing contact portions (tips) of a force terminal (contact terminal) and a sense terminal (contact terminal) held by a probe card (first card) to come into contact with an electrode terminal of a semiconductor wafer. In the step of performing the electrical test, the contact portions of the force terminal and the sense terminal move in a direction away from each other after coming into contact with the first electrode terminal.

This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.

This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.

Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a substrate and having channel, source, and drain regions. The method includes forming a well in the semiconductor layer to have a first dopant, and implanting a second dopant into the well. The first and second dopants are of opposite doping types. A first portion of the well has a higher concentration of the second dopant than the first dopant. A second portion of the well under the first portion has a higher concentration of the first dopant than the second dopant. The method further includes forming a gate stack over the channel region, and forming source and drain features in the source and drain regions. The first portion of the well electrically connects the source and drain features.

A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.

A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer.

An integrated inductor structure includes a capacitor, a guard ring, a patterned shield, and an inductor. The guard ring is coupled to the capacitor. The patterned shield is coupled to the guard ring through the capacitor, such that the patterned shield is floating. The inductor is disposed above the guard ring and the patterned shield.

An integrated inductor structure includes a capacitor, a guard ring, a patterned shield, and an inductor. The guard ring is coupled to the capacitor. The patterned shield is coupled to the guard ring through the capacitor, such that the patterned shield is floating. The inductor is disposed above the guard ring and the patterned shield.