A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming a plurality of capacitor contacts on a substrate; forming a dielectric layer on the plurality of capacitor contacts; removing portions of the dielectric layer to form a plurality of openings in the dielectric layer; exposing the plurality of capacitor contacts at bottoms of the plurality of the corresponding openings; and depositing conductive material to form a plurality of interconnects in the plurality of corresponding openings.

A semiconductor device includes; cell transistors on a substrate, lower electrodes respectively connected to the cell transistors, arranged according to a first pitch in a first horizontal direction, and extending in a vertical direction, and an etching stop layer surrounding lower sidewalls of the lower electrodes and arranged at a level higher than a level of the cell transistors, wherein the etching stop layer includes a first portion vertically overlapping the lower electrodes and a second portion laterally surrounding the first portion, and the second portion includes recesses arranged according to a second pitch in the first horizontal direction.

A monolithic integrated electro-optical phase modulator, a Mach-Zehnder modulator including one or more of the phase modulators, and method for fabricating the phase modulator by III-V-on-silicon semiconductor processing are provided. The phase modulator includes a silicon-based n-type substrate base layer, and a III-V n-type ridge waveguide for propagating light, wherein the ridge waveguide protrudes from and extends along the n-type substrate base layer. Further, the phase modulator includes one or more insulating layers provided on the ridge waveguide, wherein the one or more insulating layers have together a thickness of 1-100 nm, and a silicon-based p-type top cover layer provided on the one or more insulating layers at least above the ridge waveguide.

A monolithic integrated electro-optical phase modulator, a Mach-Zehnder modulator including one or more of the phase modulators, and method for fabricating the phase modulator by III-V-on-silicon semiconductor processing are provided. The phase modulator includes a silicon-based n-type substrate base layer, and a III-V n-type ridge waveguide for propagating light, wherein the ridge waveguide protrudes from and extends along the n-type substrate base layer. Further, the phase modulator includes one or more insulating layers provided on the ridge waveguide, wherein the one or more insulating layers have together a thickness of 1-100 nm, and a silicon-based p-type top cover layer provided on the one or more insulating layers at least above the ridge waveguide.

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.

The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.