Patent classifications
H01L31/035263
Superlattice photo detector
A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.
Semiconductor Body
A semiconductor body is disclosed. In an embodiment a semiconductor body includes an n-doped region comprising a first layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their doping concentration, and wherein the first and second layers of each pair have the same material composition except for their doping and a second layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their material composition, an active region, wherein the second layer sequence is disposed between the first layer sequence and the active region and a p-doped region, wherein the active region is disposed between the n-doped region and the p-doped region.
Semiconductor chip
A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24). A period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and a doped second semiconductor layer (22), wherein an electronic band gap E.sub.2 of the doped second semiconductor layer (22) is larger than an electronic band gap E.sub.1 of the undoped first semiconductor layer (21).
Electronic Devices Comprising N-Type and P-Type Superlattices
A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.
Tunneling barrier infrared detector devices
Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.
Superlattice-based detector systems and methods
Techniques are disclosed for facilitating detection of electromagnetic radiation using superlattice-based detector systems and methods. In one example, an infrared detector includes a first superlattice structure including first periods. Each of the first periods includes a first sub-layer and a second sub-layer adjacent to the first sub-layer. The first and second sub-layers include first and second semiconductor materials. The infrared detector further includes a second superlattice structure disposed on the first superlattice structure. The second superlattice structure includes second periods. Each of the second periods includes a third sub-layer and a fourth sub-layer adjacent to the third sub-layer. The third-sub-layer includes a third semiconductor material. The fourth sub-layer includes a fourth semiconductor material. A p-n junction is formed at an interface within the second superlattice structure or at an interface between the first and second superlattice structures.
Electronic devices comprising N-type and P-type superlattices
A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.
Tunneling barrier infrared detector devices
Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.
Tunneling barrier infrared detector devices
Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.
SEMICONDUCTOR CHIP
A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24). A period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and a doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E.sub.1 of the undoped first semiconductor layer (21).