Patent classifications
H01L31/0725
SOLAR CELL, METHOD FOR MANUFACTURING SOLAR CELL, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND PHOTOVOLTAIC POWER GENERATION SYSTEM
A solar cell of an embodiment includes a p-electrode, a p-type light-absorbing layer containing a cuprous oxide and/or a complex oxide of cuprous oxides on the p-electrode, an n-type layer on the p-type light-absorbing layer, and an n-electrode, when a first region is a region of the p-type light-absorbing layer from an interface between the p-type light absorbing layer and n-type layer to a depth of 10 nm toward the p-electrode and a second region is a region of the p-type light-absorbing layer from the interface between the p-type light absorbing layer and the n-type layer to a depth of 100 nm toward the p-electrode excluding the first region, a maximum intensity of an intensity profile of a HAADF-STEM image of the first region is 95% or more and 105% or less of an average intensity of an intensity profile of a HAADF-STEM of the second region.
MULTIJUNCTION METAMORPHIC SOLAR CELLS
A multijunction solar cell in accordance with an example implementation includes a growth substrate; a first solar subcell disposed over or in the growth substrate; a tunnel diode disposed over the first solar subcell; and a grading interlayer directly disposed over the tunnel diode; a sequence of layers of semiconductor material forming a solar cell disposed over the grading interlayer comprising a plurality of solar subcells. The multijunction solar cell also includes a first wafer bowing inhibition layer disposed directly over an uppermost sublayer of the grading interlayer, such bowing inhibition layer having an in-plane lattice constant greater than the in-plane lattice constant of the uppermost sublayer of the grading interlayer. A second wafer bowing inhibition layer is disposed directly over the first wafer bowing inhibition layer.
MULTIJUNCTION METAMORPHIC SOLAR CELLS
A multijunction solar cell in accordance with an example implementation includes a growth substrate; a first solar subcell disposed over or in the growth substrate; a tunnel diode disposed over the first solar subcell; and a grading interlayer directly disposed over the tunnel diode; a sequence of layers of semiconductor material forming a solar cell disposed over the grading interlayer comprising a plurality of solar subcells. The multijunction solar cell also includes a first wafer bowing inhibition layer disposed directly over an uppermost sublayer of the grading interlayer, such bowing inhibition layer having an in-plane lattice constant greater than the in-plane lattice constant of the uppermost sublayer of the grading interlayer. A second wafer bowing inhibition layer is disposed directly over the first wafer bowing inhibition layer.
Inverted metamorphic multijunction solar cell with surface passivation
A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.
Inverted metamorphic multijunction solar cell with surface passivation
A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.
DILUTE NITRIDE BISMIDE SEMICONDUCTOR ALLOYS
High efficiency dilute nitride bismide alloys and multijunction photovoltaic cells incorporating the high efficiency dilute nitride bismide alloys are disclosed. Bismuth-containing dilute nitride subcells exhibit a high efficiency across a broad range of irradiance energies, a high short circuit current density, and a high open circuit voltage.
DILUTE NITRIDE BISMIDE SEMICONDUCTOR ALLOYS
High efficiency dilute nitride bismide alloys and multijunction photovoltaic cells incorporating the high efficiency dilute nitride bismide alloys are disclosed. Bismuth-containing dilute nitride subcells exhibit a high efficiency across a broad range of irradiance energies, a high short circuit current density, and a high open circuit voltage.
OPTOELECTRONIC DEVICE
The invention provides an optoelectronic device comprising a photoactive region, which photoactive region comprises: an n-type region comprising at least one n-type layer; a p- type region comprising at least one p-type layer; and, disposed between the n-type region and the p-type region: a layer of a perovskite semiconductor without open porosity. The perovskite semiconductor is generally light-absorbing. In some embodiments, disposed between the n-type region and the p-type region is: (i) a first layer which comprises a scaffold material, which is typically porous, and a perovskite semiconductor, which is typically disposed in pores of the scaffold material; and (ii) a capping layer dis -posed on said first layer, which capping layer is said layer of a perovskite semiconductor without open porosity, wherein the perovskite semiconductor in the capping layer is in contact with the perovskite semiconductor in the first layer. The layer of the perovskite semiconductor without open porosity (which may be said capping layer) typically forms a planar heterojunction with the n-type region or the p-type region. The invention also provides processes for producing such optoelectronic devices which typically involve solution deposition or vapour deposition of the perovskite. In one embodiment, the process is a low temperature process; for instance, the entire process may be performed at a temperature or temperatures not exceeding 150° C.
OPTOELECTRONIC DEVICE
The invention provides an optoelectronic device comprising a photoactive region, which photoactive region comprises: an n-type region comprising at least one n-type layer; a p- type region comprising at least one p-type layer; and, disposed between the n-type region and the p-type region: a layer of a perovskite semiconductor without open porosity. The perovskite semiconductor is generally light-absorbing. In some embodiments, disposed between the n-type region and the p-type region is: (i) a first layer which comprises a scaffold material, which is typically porous, and a perovskite semiconductor, which is typically disposed in pores of the scaffold material; and (ii) a capping layer dis -posed on said first layer, which capping layer is said layer of a perovskite semiconductor without open porosity, wherein the perovskite semiconductor in the capping layer is in contact with the perovskite semiconductor in the first layer. The layer of the perovskite semiconductor without open porosity (which may be said capping layer) typically forms a planar heterojunction with the n-type region or the p-type region. The invention also provides processes for producing such optoelectronic devices which typically involve solution deposition or vapour deposition of the perovskite. In one embodiment, the process is a low temperature process; for instance, the entire process may be performed at a temperature or temperatures not exceeding 150° C.
Manufacturing Semiconductor-Based Multi-Junction Photovoltaic Devices
Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing process and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.