A quantum efficiency test controller (QETC) and related techniques for measuring quantum efficiency are described. The QETC performs one or more test iterations to obtain test results regarding quantum efficiency of a multijunction photovoltaic device (MPD) having a number N of photovoltaic junctions (N>0), where the QETC is associated with N bias light sources. During a test iteration, the QETC activates a grating monochromator to emit a first test probe of monochromatic light at a first wavelength; and while the grating monochromator is emitting the first test probe, iterates through and activates each of the N bias light sources to emit a corresponding bias band of wavelengths of light. After performing the test iteration(s), the QETC generates an output that is based on the test results related to the quantum efficiency of the MPD.

A voltage matched multijunction solar cell having first and second solar cell stacks that are electrically connected parallel to each other. The first solar cell stack is optimized for absorption of incoming solar light in a first wavelength range and the second solar cell stack is optimized for absorption of incoming solar light in a second wavelength range, wherein the first and the second wavelength range do not or at most only partially overlap each other.

A voltage matched multijunction solar cell having first and second solar cell stacks that are electrically connected parallel to each other. The first solar cell stack is optimized for absorption of incoming solar light in a first wavelength range and the second solar cell stack is optimized for absorption of incoming solar light in a second wavelength range, wherein the first and the second wavelength range do not or at most only partially overlap each other.

A solar cell comprising a bulk germanium silicon growth substrate; a diffused photoactive junction in the germanium silicon substrate; and a sequence of subcells grown over the substrate, with the first grown subcell either being lattice matched or lattice mis-matched to the growth substrate.

A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

A solar cell stack having a first semiconductor solar cell that has a p-n junction of a first material with a first lattice constant and a second semiconductor solar cell that has a p-n junction of a second material with a second lattice constant. The solar cell stack has a metamorphic buffer that includes a sequence of a first, lower layer and a second, center layer, and a third, upper layer, and includes an InGaAs or an AlInGaAs or an InGaP or an AlInGaP compound. The metamorphic buffer is formed between the first and second semiconductor solar cells and the lattice constant in the metamorphic buffer changes along the buffer's thickness dimension. The lattice constant of the third layer is greater than the lattice constant of the second layer, and the lattice constant of the second layer is greater than the lattice constant of the first layer.

A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.

[Problem] The present invention provides a method for bonding semiconductor elements while assuring excellent electric conductivity and transparency at an interface, and a junction structure according to the bonding method. The present invention also provides a method for bonding semiconductor elements wherein excellent electric conductivity is assured at an interface and optical characteristics favorable for element characteristics can be designed, and a junction structure according to the bonding method. [Solution] Electrically conductive nano particles which are not covered with organic molecules are arrayed on a surface of one semiconductor element without causing optical loss, and another semiconductor element is pressure-bonded thereagainst.