A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.

A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.

Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

A tandem photovoltaic device includes: a tunnel junction between an upper cell unit and a lower cell unit. The lower cell unit is a crystalline silicon cell. The tunnel junction includes: a carrier transport layer, a crystalline silicon layer, and an intermediate layer located between the carrier transport layer and the crystalline silicon layer. The carrier transport layer is a metal oxide layer. The intermediate layer includes a tunneling layer. The crystalline silicon layer has a doping concentration greater than or equal to 10.sup.17 cm.sup.?3. The carrier transport layer is in direct contact with a shadow surface of the upper cell unit. If the crystalline silicon layer is a p-type crystalline silicon layer, a first energy level is close to a second energy level. If the crystalline silicon layer is an n-type crystalline silicon layer, a third energy level is close to a fourth energy level.

A tandem photovoltaic device includes: a tunnel junction between an upper cell unit and a lower cell unit. The lower cell unit is a crystalline silicon cell. The tunnel junction includes: a carrier transport layer, a crystalline silicon layer, and an intermediate layer located between the carrier transport layer and the crystalline silicon layer. The carrier transport layer is a metal oxide layer. The intermediate layer includes a tunneling layer. The crystalline silicon layer has a doping concentration greater than or equal to 10.sup.17 cm.sup.?3. The carrier transport layer is in direct contact with a shadow surface of the upper cell unit. If the crystalline silicon layer is a p-type crystalline silicon layer, a first energy level is close to a second energy level. If the crystalline silicon layer is an n-type crystalline silicon layer, a third energy level is close to a fourth energy level.

The present disclosure pertains to the field of back contact cell technologies, and particularly relates to a hybrid passivation back contact cell and a fabrication method thereof, the hybrid passivation back contact cell including: an N-type doped silicon substrate having a light receiving surface and a back surface, and a first semiconductor layer and a second semiconductor layer which are arranged on the back surface, wherein the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer sequentially arranged in an outward direction perpendicular to the back surface, and the first semiconductor layer includes a tunneling oxide layer and an N-type doped silicon crystal layer sequentially arranged in the outward direction perpendicular to the back surface.

The present disclosure pertains to the field of back contact cell technologies, and particularly relates to a hybrid passivation back contact cell and a fabrication method thereof, the hybrid passivation back contact cell including: an N-type doped silicon substrate having a light receiving surface and a back surface, and a first semiconductor layer and a second semiconductor layer which are arranged on the back surface, wherein the second semiconductor layer includes an intrinsic silicon layer and a P-type doped silicon layer sequentially arranged in an outward direction perpendicular to the back surface, and the first semiconductor layer includes a tunneling oxide layer and an N-type doped silicon crystal layer sequentially arranged in the outward direction perpendicular to the back surface.

A solar cell comprising a silicon substrate and a layered structure arranged on a surface of the silicon substrate, the layered structure comprising; a first layer comprising a percentage of crystalline material arranged within an amorphous matrix, the first layer being arranged on the surface of the silicon substrate; a second layer comprising a percentage of crystalline material arranged within an amorphous matrix, the second layer being interposed between the first layer and the surface of the silicon substrate; wherein the percentage of crystalline material in the first layer is greater than the percentage of crystalline material in the second layer.