A multi junction photodiode for molecular detection and discrimination and fabrication methods thereof. The multi junction photodiode includes a substrate having first conductive type dopants, an epitaxial layer having the first conductive type dopants, a deep well having second conductive type dopants, a first well having the first conductive type dopants, a second well having the second conductive type dopants, a third well having the first conductive type dopants, and a first doped region having the second conductive type dopants. The epitaxial layer is disposed on the substrate. The deep well is disposed in the epitaxial layer. The first well having three sides connected to the epitaxial layer is disposed in the deep well. The second well is disposed in the first well. The third well having three sides connected to the epitaxial layer is disposed in the second well. The first doped region is disposed in the third well.

A multi junction photodiode for molecular detection and discrimination and fabrication methods thereof. The multi junction photodiode includes a substrate having first conductive type dopants, an epitaxial layer having the first conductive type dopants, a deep well having second conductive type dopants, a first well having the first conductive type dopants, a second well having the second conductive type dopants, a third well having the first conductive type dopants, and a first doped region having the second conductive type dopants. The epitaxial layer is disposed on the substrate. The deep well is disposed in the epitaxial layer. The first well having three sides connected to the epitaxial layer is disposed in the deep well. The second well is disposed in the first well. The third well having three sides connected to the epitaxial layer is disposed in the second well. The first doped region is disposed in the third well.

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

According to one embodiment, a semiconductor device 100 includes a semiconductor substrate 1 including a first principal surface and a second principal surface, an emitter electrode 46, a gate wiring 49, a collector electrode 43, a first unit cell region 10 that is extended along one direction in a plane parallel to the first principal surface, and a second unit cell region 20 that is extended along one direction, in which the semiconductor substrate 1 of the first unit cell region 10 and the second unit cell region 20 includes an N type drift layer 39, an N type hole barrier layer 38, a trench electrode 13, a P type body layer 36, an insulating film 35, an N type field stop layer 41, and a P+ type collector layer 42, and the second unit cell region 20 includes an N type cathode layer 47 that is fitted into the collector layer 42 and is extended along one direction.

A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n.sup.+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n.sup.+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n.sup.+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

A semiconductor device includes a semiconductor body including a base region and two semiconductor mesas separated from each other by an insulated trench gate structure extending from a first side into the base region, and including a dielectric layer separating a gate electrode from the semiconductor body. Each semiconductor mesa includes, in a cross-section perpendicular to the first side, a body region forming a pn-junction with the base region, a latch-up-safety region of the same conductivity type as the body region arranged between the body region and the first side, and having a higher doping concentration than the body region, and an emitter region between the dielectric layer and the latch-up-safety region and forming a pn-junction with the body region. At least one semiconductor mesa includes an emitter contact arranged between the emitter region and the latch-up-safety region and forming with the latch-up-safety and emitter regions an Ohmic contact.

An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n.sup.+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n.sup.+-type emitter regions are arranged in a staggered configuration in plan view.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

A layered structure includes a thyristor and a light-emitting element. The thyristor at least includes four layers. The four layers are an anode layer, a first gate layer, a second gate layer, and a cathode layer arranged in this order. The light-emitting element is disposed such that the light-emitting element and the thyristor are connected in series. The thyristor includes a semiconductor layer having a bandgap energy smaller than bandgap energies of the four layers.