Methods and apparatus for processing a photonic device are provided herein. For example, methods include etching, using a plasma etch process that uses a first gas, a first epitaxial layer of material of the photonic device comprising a base layer comprising at least one of silicon, germanium, sapphire, aluminum indium gallium arsenide (Al.sub.xIn.sub.yGa.sub.1-x-yAs), aluminum indium gallium phosphide (Al.sub.xIn.sub.yGa.sub.1-x-yP), aluminum indium gallium nitride (Al.sub.xIn.sub.yGa.sub.1-x-yN), aluminum indium gallium arsenide phosphide (Al.sub.xIn.sub.yGa.sub.1-x-yAs.sub.zP.sub.1-z), depositing, using a plasma deposition process that uses a second gas different from the first gas, a first dielectric layer over etched sidewalls of the first epitaxial layer of material, etching, using the first gas, a second epitaxial layer of material of the photonic device, and depositing, using the second gas, a second dielectric layer over etched sidewalls of the second epitaxial layer of material.

A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.

A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a first layer, a second layer and an active layer arranged between the first layer and the second layer, the semiconductor layer sequence having at least one injection region, wherein the first layer includes a first conductivity type, wherein the second layer includes a second conductivity type, wherein the semiconductor layer sequence includes the first conductivity type within the entire injection region, wherein the injection region, starting from the first layer, at least partially penetrates the active layer, wherein side surfaces of the semiconductor layer sequence are formed at least in places by the injection region, and wherein the injection region is configured to inject charge carriers directly into the active layer.

A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters includes the following steps: providing a relaxation substrate that comprises a medium, a flow layer disposed on the medium and, a plurality of strained crystalline semiconductor islands having an initial lattice parameter located on the flow layer, a first group of islands having a first lattice parameter and a second group of islands having a second lattice parameter that is different from the first; and heat treating the relaxation substrate at a relaxation temperature greater than or equal to the glass transition temperature of the flow layer to cause differentiated lateral expansion of the islands of the first and second group. The lattice parameter of the relaxed islands of the first group and the relaxed islands of the second group then have different values.

The present invention relates to a betavoltaic battery comprising: a substrate; an intrinsic semiconductor unit disposed on the substrate; an N-type semiconductor unit and a P-type semiconductor unit that are disposed on at least a portion of a surface of the intrinsic semiconductor unit and arranged alternately; and beta ray sources that are disposed on the N-type semiconductor unit and the P-type semiconductor unit. The present invention also relates to a method for manufacturing a betavoltaic battery, comprising the steps of: (A) forming an intrinsic semiconductor unit on a substrate; (B) forming an N-type semiconductor unit and a P-type semiconductor unit alternately by irradiating at least a portion of the surface of the intrinsic semiconductor unit with an ion beam; and (C) disposing a beta ray source on the N-type semiconductor unit and the P-type semiconductor unit.

A metamorphic multijunction solar cell having a growth semiconductor substrate with a top surface having a doping in the range of 1x10.sup.18 to 1x10.sup.20 charge carriers/cm.sup.3; a window layer for a top (light facing) subcell formed directly on the top surface of the growth substrate; a sequence of layers of semiconductor material forming a solar cell directly on the window layer; a surrogate substrate on the top surface of the sequence of layers of semiconductor material, wherein a portion of the semiconductor substrate is removed so that only the high doped surface portion of the substrate, having a thickness in the range of 0.5 μm to 10 μm, remains.

A method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate.

The present disclosure provides a method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate.

A composition of matter comprising: a graphene layer carried directly on a sapphire, Si, SiC, Ga.sub.2O.sub.3 or group III-V semiconductor substrate; wherein a plurality of holes are present through said graphene layer; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowires or nanopyramids comprising at least one semiconducting group III-V compound.