A process for producing a structure (100) comprising a membrane (3) of a first material, in particular indium-tin oxide, in contact with receiving ends (13) of a plurality of nanowires (1), the process comprising

forming a nanowire device (10) comprising the receiving ends (13), the receiving ends being formed so as to form planar

surfaces, and (ii) placing, especially by transfer, a membrane device (3; 34) directly on the nanowires the planar surfaces of the ends for receiving the membrane.

An optoelectronic semiconductor chip and a method for manufacturing a semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a plurality of fins and a current expansion layer for common contacting of at least some of the fins, wherein each fin includes two side surfaces arranged opposite one another and an active region arranged on each of the side surfaces, wherein the plurality of fins include inner fins and outer fins having an adjacent fin only on one side, and wherein the current expansion layer is in direct contact with the inner fins on their outside.

A micro LED display and a manufacturing method thereof are disclosed. A plurality of electrode structures is formed on a first surface of a substrate, and a plurality of circuit structure are formed in the substrate, where the circuit structures are electrically connected to the electrode structures. An LED functional layer is formed on the substrate, and includes a plurality of mutually isolated LED functional structures, where the LED functional structures are corresponding and electrically connected to the electrode structures. An electrode layer covers the LED functional layer and is electrically connected to the LED functional structures. Micro lenses are formed on the electrode layer and corresponding to the LED functional structures. Therefore, all the LED functional structures can be wholly used as a light-emitting region of a pixel, improving light emission efficiency of the micro LED display.

A light emitting device package includes a cell array having a first surface and a second surface located opposite to the first surface and including, on a portion of a horizontal extension line of the first surface, semiconductor light emitting units each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially located on a layer surface including a sidewall of the first conductivity type semiconductor layer; wavelength converting units corresponding respectively to the semiconductor light emitting units and each arranged corresponding to the first conductivity type semiconductor layer; a barrier structure arranged between the wavelength converting units corresponding to the cell array; and switching units arranged in the barrier structure and electrically connected to the semiconductor light emitting units.

The invention relates to a process for fabricating at least one semiconductor structure (20) separated from a support substrate (11), comprising the following steps: producing a two-dimensional nucleation layer (13) starting from the support substrate (11), producing the semiconductor structure (20) by epitaxy starting from the nucleation layer, obtaining a first electrode (30) located in a lateral zone (3) which borders the semiconductor structure; placing the structure thus obtained in an aqueous electrolytic bath (50); applying a potential difference between the electrodes (30, 40) until the separation of the semiconductor structure (20) relative to the support substrate (11) is brought about.

Embodiments generally relate to micro-device arrays. In some embodiments, an array comprises a substrate and a plurality of micro-devices. Each micro-device is suspended over a cavity in the substrate by at least one lateral hinge attached to a side post formed into the substrate. Each micro-device comprises a bonding layer; a metal contact; semiconductor device layers; and a buffer layer. The semiconductor device layers may comprise GaN-based LED layers; wherein the buffer layer comprises AlGaN; and wherein the substrate comprises (111) oriented Silicon. In other cases, the semiconductor device layers may comprise InGaAsP-based LED layers; wherein the buffer layer comprises InGaP; and wherein the substrate comprises GaAs.

An LED wafer processing method includes a dividing step of rotatably mounting a first cutting blade having a first width in a first cutting unit, holding an LED wafer on a holding table, and then relatively moving the first cutting unit and the holding table to cut the wafer along each division line formed on the wafer, thereby forming a full-cut groove along each division line to thereby divide the wafer into individual chips. The method further includes rotatably mounting a second cutting blade having a second width larger than the first width in a second cutting unit after performing the dividing step, and then relatively moving the second cutting unit and the holding table to thereby polish the opposed side surfaces of the full-cut groove formed along each division line, whereby a polished groove larger in width than the full-cut groove is formed along each full-cut groove.

A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.

A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.