A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111>oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer. Electronic devices such as LEDs can be manufactured from such structures. Because the substrate can act as both a reflector and a heat sink, transfer to other substrates, and use of external reflectors and heat sinks, is not required, greatly reducing costs. Large area devices such as light emitting strips or sheets may be fabricated using this technology.

A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.

The present disclosure relates to a light-emitting device, display device including the same, and method for manufacturing the same. A light-emitting device includes a nitride semiconductor structure including a first semiconductor layer, an active layer and a second semiconductor layer; and a passivation pattern at least partially surrounding an outer side surface of the nitride semiconductor structure, wherein the nitride semiconductor comprises a convex hemispherical shape.

A method of manufacturing an electronic device, including the successive steps of: a) performing an ion implantation of indium or of aluminum into an upper portion of a first single-crystal gallium nitride layer, to make the upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a crystalline indium gallium nitride or aluminum gallium nitride layer.

A semiconductor substrate includes a heterogeneous substrate, a mask layer having an opening portion and a mask portion, a seed portion overlapping the opening portion, and a semiconductor layer including a GaN-based semiconductor and disposed on the seed portion and the mask portion. An upper surface of an effective portion of the semiconductor layer includes at least one low-level defective region with a size of 10 ?m in a first direction along a width direction of the opening portion and 10 ?m in a second direction orthogonal to the first direction, and a line defect is not measured by a CL method in the low-level defective region.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (Ni.sub.xMg.sub.yZn.sub.1-x-y).sub.2GeO.sub.4 wherein 0x1 and 0y1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.

The present disclosure provides a semiconductor structure, including: a substrate, a first-type mask layer, a second-type mask layer, and an epitaxial layer; where the first-type mask layer includes a first mask multilayer, the first mask multilayer includes a first mask layer and a second mask layer, the first mask layer includes a first window, the second mask layer includes a second window communicating with the first window, the second window and the first window constitute a first-type window, and a cross-section of the second window is larger than that of the first window; the second-type mask layer is located on a side of the first-type mask layer away from the base; the second-type mask layer includes a second-type window communicating with the first-type window, and a cross-section of the second-type window is smaller than that of the second window.

An epitaxial structure of a light-emitting device and a manufacturing method thereof are provided. The epitaxial structure of the light-emitting device includes a first semiconductor layer, an active region and a second semiconductor layer sequentially stacked; where the active region includes at least one group of a barrier layer and a quantum well layer which are stacked, a surface of the quantum well layer away from the first semiconductor layer has a first roughness, a surface of the barrier layer away from the first semiconductor layer has a second roughness, and the first roughness is greater than the second roughness.

A light emitting device includes: a substrate; a DBR mask layer on a side of the substrate, the DBR mask layer being provided with a window exposing the substrate, the window including an opening end away from the substrate and a bottom wall end close to the substrate, and on a plane where the substrate is located, an orthographic projection of the opening end falling within an orthographic projection of the bottom wall end; and a light emitting unit. The light emitting unit includes an active layer located on a side, away from the substrate, of the DBR mask layer. Providing the window on the DBR mask layer may reduce dislocation density during epitaxial growth of the light emitting unit, and arrangement of the DBR mask layer may improve light extraction efficiency of the light emitting device.

A light emitting device including a substrate having a light emitting area and a light shielding area, a light emitting structure disposed on the substrate and comprising at least one active layer, and a light shielding layer disposed on the substrate and defining the light shielding area, in which the light emitting area overlaps with the light emitting structure, the substrate has a rough surface overlapping at least a portion of the light emitting area, and a portion of the rough surface is covered with the light shielding layer, and light emitted from the at least one active layer is configured to be transmitted through the substrate.