The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material, beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5 × 10.sup.17 cm.sup.-3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

The present invention provides an assembly substrate used in a method for manufacturing a display device which mounts semiconductor light emitting devices on a predetermined position of an assembly substrate by using an electric field and a magnetic field. Specifically, the assembly substrate is characterized by comprising: a base part; a plurality of assembly electrodes formed extending in one direction and disposed on the base part; a dielectric layer laminated on the base part so as to cover the assembly electrodes; a partition wall formed on the base part and including a plurality of grooves for guiding the semiconductor light emitting devices to a predetermined position; and a metal shielding layer formed on the base part, wherein each of the plurality of grooves penetrates the partition wall so as to form a seating surface on which the guided light emitting devices are seated, and the metal shielding layer overlaps with a part of the seating surface such that an electric field formed on a part of the seating surface is shielded.

A method for manufacturing an image display device according to an embodiment includes preparing a structure including a semiconductor layer formed on a first substrate, bonding the semiconductor layer to a first surface of a second substrate, removing the first substrate, forming a light-emitting element including a light-emitting surface opposite to a bottom surface on the first surface by etching the semiconductor layer, forming a first insulating film that covers the first surface and the light-emitting element, forming a circuit element on the first insulating film, forming a second insulating film that covers the circuit element and the first insulating film, exposing a surface including the light-emitting surface by removing a portion of the first and second insulating films, forming a via extending through the first and second insulating films, and forming a wiring layer on the second insulating film.

An epitaxial structure, a preparation method thereof, and a light-emitting diode (LED) are provided. The epitaxial structure includes a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence.

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the method, for the substrate, the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer distributed sequentially from bottom to top, the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in first predetermined regions are removed to form grooves. The second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in second predetermined regions and third predetermined regions are retained. Layers retained in second predetermined regions form light emitting units arranged in an array. Various layers retained in third predetermined regions form connection posts, each of which connects adjacent light emitting units. Widths of the third predetermined region are smaller than widths of the second predetermined region in the lateral and longitudinal direction of the array.

A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5×10.sup.17 cm.sup.−3, beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.

The application relates to a substrate structure, an on-chip structure, and a method for manufacturing the on-chip structure. The substrate structure includes a substrate body and an electrothermal layer. The electrothermal layer is arranged on a surface of the substrate body for growing an epitaxial layer. In an actual lift off process of the epitaxial layer, only the electrothermal layer is electrically conducted to an external power supply via an electrode, and heating of the electrothermal layer is utilized to heat the epitaxial layer, therefore, a part of the epitaxial layer in contact with the substrate structure can be thermally decomposed and separated from the substrate structure.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a first epitaxial semiconductor layer on the substrate; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The first epitaxial semiconductor layer can comprise a first oxide material, wherein the first oxide material can comprise a first polar material with an orthorhombic, tetragonal or trigonal crystal symmetry, and wherein the first oxide material can comprise a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Described are light emitting diode (LED) devices having a patterned dielectric layer on a substrate and methods for effectively growing epitaxial III-nitride layers on them. A nucleation layer, comprising a III-nitride material, is grown on a substrate before any patterning takes place. The patterned dielectric layer comprises a first plurality of features and a second plurality of features, where the second plurality of features has a height larger than the height of the first plurality of features. The second plurality of features aligns with the cathode layer of the trench.