A semiconductor substrate structure includes a seed layer on a substrate, a first gallium nitride layer on the seed layer, and a patterned first hard mask layer on the first gallium nitride layer, wherein the patterned first hard mask layer includes a first opening. The semiconductor substrate structure also includes a second gallium nitride layer in the first opening and on the patterned first hard mask layer, a patterned second hard mask layer on the second gallium nitride layer, wherein the patterned second hard mask layer includes a second opening, and at least a portion of a projection on the substrate of the first opening and a projection on the substrate of the second opening are non-overlapped. The semiconductor substrate structure further includes a third gallium nitride layer in the second opening and on the patterned second hard mask layer.

A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 μm and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.

Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

On an RAMO.sub.4 substrate containing a single crystal represented by the general formula RAMO.sub.4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Light emitting devices and methods of manufacturing the light emitting devices. The light emitting devices include a silicon substrate; a metal buffer layer on the silicon substrate, a patterned distributed Bragg reflector (DBR) on the metal buffer layer; and a nitride-based thin film layer on the patterned DBR and regions between patterns of the DBR.

A method for repairing etching damage on a nitride-based epitaxial layer of an optoelectronic device and an optoelectronic device attributable thereto are provided. The method includes: providing a nitrogen-containing working liquid and a annealing apparatus having a reaction chamber; heating the reaction chamber to a predetermined temperature; atomizing the nitrogen-containing working liquid, and introducing the thus formed nitrogen-containing spray into the reaction chamber; and subjecting the optoelectronic device to an annealing treatment in the reaction chamber in the presence of the nitrogen-containing spray, so as to repair the etching damage on the nitride-based epitaxial layer.

A method of fabricating an active matrix display is disclosed in which one or more oxide thin film transistors is monolithically integrated with an inorganic light emitting diode structure. The method comprises forming an array of inorganic light emitting diodes over a substrate defining a plurality of sub-pixels, depositing an insulating layer over the inorganic LED array, forming conductive vias through the insulating layer, one via for each LED in the LED array, and forming a metal oxide thin film transistor backplane, including an array of pixel driver circuits, over the dielectric layer and conductive vias, wherein one driver circuit electrically controls each sub-pixel through the dielectric layer.

A light emitting device, such as an LED, is formed by forming a plurality of semiconductor nanostructures having a doping of a first conductivity type through, and over, a growth mask layer overlying a doped compound semiconductor layer. Each of the plurality of semiconductor nanostructures includes a nanofrustum including a bottom surface, a top surface, tapered planar sidewalls, and a height that is less than a maximum lateral dimension of the top surface, and a pillar portion contacting the bottom surface of the nanofrustum and located within a respective one of the openings through the growth mask layer. A plurality of active regions on the nanofrustums. A second conductivity type semiconductor material layer is formed on each of the plurality of active regions.

A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.