The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Disclosed are a light emitting diode and a method for manufacturing a light emitting diode. The light emitting diode includes a first-type layer, a light emitting layer, a second-type layer and an electrode layer; the first-type layer includes a first-type gallium nitride; the light emitting layer is located on the first-type layer; the light emitting layer includes a quantum point; the second-type layer is located on the light emitting layer; the second-type layer includes a second-type gallium nitride or an indium tin oxide; and the electrode layer is located on the second-type layer.

The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1−x1−yl).sub.2GeO.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1. In some cases, either: x1≠x2 and y1=y2; x1=x2 and y1≠y2; or x1≠x2 and y1≠y2. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Mg.sub.x1Zn.sub.1−x1)(Al.sub.y1Ga.sub.1−y1).sub.2O.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1.

In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 10.sup.19 cm.sup.−3.

A method of manufacturing a light-emitting device, including: providing a substrate structure including a base portion and wherein the base portion includes a surface; performing a patterning step to form a plurality of protrusions, wherein the plurality of protrusions are arranged on the surface of the base portion; forming a buffer layer on the surface of the base portion by physical vapor deposition, wherein the buffer layer covers the protrusions; and forming III-V compound semiconductor layers on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 μm; and wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve.

Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

A light-emitting diode (LED) device includes a substrate, an epitaxial layered structure disposed on the substrate, a current-spreading layer disposed on the epitaxial layered structure, a current-blocking unit disposed on the current-spreading layer, and a distributed Bragg reflector. The epitaxial layered structure, the current-spreading layer and the current-blocking unit are covered by the distributed Bragg reflector. One of the current-spreading layer, the current-blocking unit, and a combination thereof has a patterned rough structure. A method for manufacturing the LED device is also disclosed.

This disclosure discloses a light-emitting element having a light-emitting unit, a transparent layer and a wavelength conversion layer formed on the transparent layer. The transparent layer covers the light-emitting unit. The wavelength conversion layer includes a phosphor layer having a phosphor and a stress release layer without the phosphor

A method of producing a light emitting diode (LED) array comprises: forming a plurality of layers (100, 101, 103) of semiconductor material; forming a dielectric mask layer (104) over the plurality of layers, the dielectric mask layer having an array of holes (106) through it each exposing an area of one of the layers of semiconductor material, and growing an LED structure (110, 112, 114) in each of the holes arranged to emit light over a range of wavelengths. At least some of the plurality layers (101) form a distributed Bragg reflector (DBR) arranged to reflect light of at least some of said range of wavelengths.