A light emitting device includes a substrate, and a laminated structure provided on the substrate, wherein the laminated structure has a plurality of columnar portions, the columnar portion contains a material having a wurtzite-type crystal structure, in a plan view as seen from a layered direction of the laminated structure, the plurality of columnar portions are arranged in a square lattice form or rectangular lattice form, a line passing through centers of the adjacent columnar portions is inclined relative to m-planes of the columnar portions located between the centers of the adjacent columnar portions, and vertices of the adjacent columnar portions are not placed on the line.

Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 m or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.

A growth substrate for forming optoelectronic devices comprises a growth medium and, arranged on the growth medium, a first group of crystalline semiconductor islands having a first lattice parameter and a second group of crystalline semiconductor islands having a second lattice parameter that is different from the first. Methods may be used to manufacture such growth substrates. The methods may be used to provide a monolithic micro-panel or light-emitting diodes or a micro-display screen.

A light emitting diode (LED) chip and a method for manufacturing an LED chip are provided. The LED chip includes a sapphire layer, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a P electrode, and an N electrode. The N-type semiconductor layer, the light emitting layer, the P-type semiconductor layer, the P electrode are sequentially disposed on a surface of the sapphire layer. The sapphire layer defines multiple preset patterns which extend through the sapphire layer, and the multiple preset patterns are used for reflecting a light of a preset wavelength through a channel defined by the sapphire layer.

A method for micro-LED epitaxial wafer manufacturing and a micro-LED epitaxial wafer are provided. The method includes the following. For each growth region of a micro-LED chip on a growth substrate, photoresist is applied to the growth region. For each growth region, an epitaxial isolation wall is grown at a boundary of the growth region. For each growth region, the photoresist on the growth substrate is removed with the epitaxial isolation wall remained. For each growth region, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are grown in the growth region to obtain a micro-LED epitaxial structure. The growth substrate is cut along the epitaxial isolation wall, to obtain at least two micro-LED epitaxial structures.

A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.

A method of manufacturing an optoelectronic semiconductor chip includes providing a growth substrate, growing a semiconductor layer sequence on the growth substrate, depositing a metallization on a side of the semiconductor layer sequence remote from the growth substrate, depositing a layer on the metallization, coupling a carrier to the layer on a side of the layer remote from the semiconductor layer sequence, separating the growth substrate from the semiconductor layer sequence, depositing an electrically conductive layer on a side of the semiconductor layer sequence facing away from the carrier, separating the carrier from the layer, thereby forming a layer stack with the metallization, the semiconductor layer sequence, the electrically conductive layer and a coupling layer including at least a part of a further material of the layer remaining on a side of the metallization remote from the semiconductor layer sequence, and coupling the layer stack to a chip carrier.

An optoelectronic device configured for improved light extraction through a region of the device other than the substrate is described. A group III nitride semiconductor layer of a first polarity is located on the substrate and an active region can be located on the group III nitride semiconductor layer. A group III nitride semiconductor layer of a second polarity, different from the first polarity, can located adjacent to the active region. A first contact can directly contact the group III nitride semiconductor layer of the first polarity and a second contact can directly contact the group III nitride semiconductor layer of the second polarity. Each of the first and second contacts can include a plurality of openings extending entirely there through and the first and second contacts can form a photonic crystal structure. Some or all of the group III nitride semiconductor layers can be located in nanostructures.

A semiconductor device having a planar III-N semiconductor layer includes a substrate including a wafer and a buffer layer of a buffer material different from a material of the wafer, the buffer layer having a growth surface, an array of nanostructures epitaxially grown from the growth surface, a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T, where the number of lattice cells spanning a center distance between adjacent nanostructures are different at the growth surface and at the coalesced planar layer, and a growth layer epitaxially grown on the planar layer.

A light emitting structure that includes: first and second semiconductor layers having aluminum; and an active layer having aluminum between the first and the second semiconductor layers, the intensity exhibited in the second semiconductor layer range between a first minimum intensity of the secondary ions and a first maximum intensity of the secondary ions, and the intensity exhibited in the first semiconductor layer include a second minimum intensity of the secondary ions, the second minimum intensity being different from the first minimum intensity, and at a first prescribed distance from a surface of the second semiconductor layer, the second semiconductor layer exhibits a first intermediate intensity of the secondary ions corresponding to the second minimum intensity, which is between the first minimum intensity and the first maximum intensity, wherein the first maximum intensity occurs at a second prescribed distance from the first prescribed distance, wherein a ratio of the second prescribed distance (W1) to the first prescribed distance (W2) is within a range of 1:0.2 to 1:1.