A semiconductor device includes a contact via and a metal interconnect on the contact via. The metal interconnect has a portion extending in a lengthwise direction that is wrapped around and in contact with a sidewall of the contact via. Along a widthwise direction, the metal interconnect does not contact the sidewall of the contact via.

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.