The invention relates to a vacuum chuck for clamping workpieces (19), in particular wafers, and a measuring device and a method for checking workpieces, in particular wafers, by means of X-ray fluorescent radiation.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A method is provided for aligning micro light-emitting diodes. A platform is provided with arrays. Each of the arrays includes grooves. The platform is used to receive magnetic micro light-emitting diodes. Magnetic attraction and vibration are alternately exerted on the platform to cause the magnetic micro light-emitting diodes to fall into the grooves in a correct orientation. It is determined whether the magnetic micro light-emitting diodes fill the platform. Mass transfer is executed if the magnetic micro light-emitting diodes fill the platform.

In a processing method for a wafer with a mark formed in an outer peripheral portion thereof, a frame unit having the wafer, a tape, and a ring frame is provided, a set of processing conditions for processing the wafer is selected, and a representative image associated with the set of processing conditions is displayed on a display unit. The ring frame includes a notch formed in an outer periphery thereof. In the frame unit, the mark and the notch are in a positional relationship set in accordance with the set of processing conditions. The positional relationship is presented in the representative image.

This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to transfer the devices to receiver substrate with fewer steps.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

According to one embodiment, a method of manufacturing a display device is provided. The display device includes a mounting substrate and a plurality of light-emitting elements two-dimensionally arrayed and mounted on the mounting substrate. The plurality of light-emitting elements have a planar shape that is non-rotationally symmetric and non-linearly symmetric. The method includes preparing the plurality of light-emitting elements separated from each other, preparing an array guide member, and aligning the plurality of light-emitting elements following the two-dimensional array of the opening portion group.