H01L2221/68309

TECHNIQUES FOR DIE TILING
20230343774 · 2023-10-26 ·

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE

A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

Method of aligning micro light emitting element and display transferring structure

A method of aligning micro light emitting elements includes supplying the plurality of micro light emitting elements on a substrate including a plurality of grooves having different shapes, the plurality of micro light emitting elements being configured to be inserted exclusively and respectively into the plurality of grooves; respectively inserting the plurality of micro light emitting elements into the plurality of grooves; and aligning the plurality of micro light emitting elements, wherein at least one groove of the plurality of grooves has a shape that is different from a shape of a respective micro light emitting element inserted into the at least one groove.

DEVICE FOR SELF-ASSEMBLING SEMICONDUCTOR LIGHT-EMITTING DIODES

Discussed is a device for self-assembling semiconductor light-emitting diodes for placing the semiconductor light-emitting diodes at predetermined positions on a substrate by using an electric field and a magnetic field, the substrate being accommodated in an assembly chamber accommodating a fluid, the device including a substrate chuck configured to dispose the substrate at an assembly position, wherein the substrate chuck includes a substrate support part configured to support the substrate on which an assembly electrode is formed, a rotating part configured to support the substrate support part, and a controller configured to control driving of the substrate chuck, wherein the substrate support part includes micro-holes for injecting a gas between the fluid and the substrate, and wherein the controller controls whether the gas is injected through the micro-holes according to whether the substrate is raised or lowered.

Substrate processing method

A substrate having a first surface with at least one division line and an opposite second surface is processed by attaching a protective sheeting to the first surface and applying a laser beam to the protective sheeting to form a plurality of alignment marks in the protective sheeting. The substrate has a backside layer on the second surface. A laser beam is applied to the substrate from the side of the first surface. The substrate is transparent to the laser beam and the focal point of the laser beam is located inside the substrate which is closer to the second surface than to the first surface, to form a plurality of alignment marks in the backside layer. Substrate material is removed along the division line from the side of the second surface. The alignment marks are used for aligning the substrate material removing means relative to the division line.

TECHNIQUES FOR DIE TILING
20220238506 · 2022-07-28 ·

Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

Die attach systems, and methods of attaching a die to a substrate

A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool for contacting the die during a transfer from the die supply source to the substrate; a first motion system for moving the bond head along a first axis; and a second motion system, independent of the first motion system, for moving the bond tool along the first axis.

AN ALIGNMENT PROCESS FOR THE TRANSFER SETUP
20220223483 · 2022-07-14 · ·

A method of aligning a first substrate and a second substrate comprises positioning the first substrate having at least a first alignment mark in close proximity to the second substrate having at least a second alignment mark, measuring an alignment value between the first and second alignment marks of both the first and second substrate; and adjusting the position of the first substrate and the second substrate based on the measured alignment value.

METAL FOIL WITH CARRIER AND USE METHOD AND MANUFACTURING METHOD THEREFOR

Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.

MODULE FOR REMOVING MIS-ASSEMBLED SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR REMOVING MIS-ASSEMBLED SEMICONDUCTOR LIGHT-EMITTING ELEMENT BY USING SAME
20220254657 · 2022-08-11 · ·

According to an embodiment of the present invention, a removal module using an electric field and a magnetic field so as to self-assemble, on cells arranged in a matrix form of an assembly substrate, semiconductor light-emitting elements introduced in a fluid accommodated in a chamber, and then remove a semiconductor light-emitting element mis-assembled with the assembly substrate comprises: a fluid supply unit for supplying the fluid; and a housing of which one side is connected to the fluid supply unit, an upper plate is adjacent to the assembly substrate, and a lower plate is adjacent to the chamber, wherein the upper plate has: a nozzle hole allowing communication between the inner space of the housing and the inner space of the chamber so that the fluid supplied from the fluid supply unit is injected at a site in which the semiconductor light-emitting element is mis-assembled on the assembly substrate; and one pair of partition parts facing each other with the nozzle hole as the center thereof.