A mass transfer device includes at least one transfer cavity. Each transfer cavity is configured to accommodate a plurality of micro light-emitting diodes. Each transfer cavity includes a bottom plate and a cavity wall connecting the bottom plate. The bottom plate defines a plurality of through holes spaced apart from each other. The transfer cavity is used to transfer the plurality of micro light-emitting diodes to the array substrate of a display panel through the plurality of through holes.

A method of aligning micro light emitting elements includes supplying the plurality of micro light emitting elements on a substrate including a plurality of grooves having different shapes, the plurality of micro light emitting elements being configured to be inserted exclusively and respectively into the plurality of grooves; respectively inserting the plurality of micro light emitting elements into the plurality of grooves; and aligning the plurality of micro light emitting elements, wherein at least one groove of the plurality of grooves has a shape that is different from a shape of a respective micro light emitting element inserted into the at least one groove.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.

Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

A carrier tape may include a tape, a plurality of pockets, and a plurality of vents in each of the plurality of pockets. The plurality of vents may provide a vapor egress path for vapor that may occur during a dry bake process of the carrier tape.

Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

A device for transferring micro-devices from a holding device to a final surface, avoiding damage during the process and ensuring coplanar presentation onto the final surface, includes a first substrate on the holding device. The holding device carries at least one transfer substrate which itself carries a plurality of micro-devices. At least one buffering member is located between the first substrate and the transfer substrate. The buffering member provides a small range of buffering for the micro-devices during the transfer and also compensates for any slight unevenness when the micro-devices are laid on and bonded to the final surface. A method for transferring the micro-devices is also disclosed.

A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.