A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

The present disclosure relates to methods of forming a film including small molecules. Such methods can optionally include removing such small molecules, such as by way of sublimation, evaporation, or conversion to a more volatile form.

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

An outer circumferential region of a metal film and a portion of an outer circumferential region of a substrate on a reverse side thereof are removed, thereby exposing the outer circumferential region of the substrate and creating on a reverse side of an outer circumferential region of the wafer an exposed surface where a portion closer to a face side of a wafer is located outwardly of a portion remoter from the face side of the wafer. When a tape is affixed to a reverse side of the wafer, no gap or a reduced gap is formed between the tape and the outer circumferential region of the wafer. As a result, problems are restrained from occurring when the wafer is divided to manufacture chips therefrom.

A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.

The present invention provides a semiconductor chip delamination device for peeling off a protective film attached to one surface of a semiconductor chip, including: a stage unit (400) configured to allow a ring frame, in which the semiconductor chip having the protective film attached thereto is disposed, to be seated thereon; a delamination feeding unit (300) configured to feed a delamination seal contactable with the protective film so as to peel off the protective film from the semiconductor chip; a covering unit (500, 600) configured to allow the delamination seal to cover the semiconductor chip such that the delamination seal comes into close contact with the protective film; and a delaminating unit (700) configured to peel off, from the semiconductor chip, the delamination seal disposed to cover the semiconductor chip having the protective film disposed on one surface thereof, and provides a method of controlling the semiconductor chip delamination device.

The present disclosure relates to an adhesive tape for a semiconductor manufacturing process, the adhesive tape being attached on a lower surface of a semiconductor package on which a plurality of protrusion electrodes are formed. The adhesive tape is configured to include a first base film, a first adhesive layer containing an acrylic-based copolymer, the first adhesive layer being stacked on top of the first base film, a second base film containing a metal material in such a manner as to be deformed and then kept deformed during each process in a manner that corresponds to a topology of the lower surface of the semiconductor package, the second base film being stacked on top of the first adhesive layer, and a second adhesive layer containing silicon having a spiral network structure, the second adhesive layer being on top of the second base film.