A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

The invention provides a semiconductor substrate cleaning method including a step of removing an adhesive layer provided on a semiconductor substrate by use of a remover composition, wherein the remover composition contains a solvent but no salt; and the solvent includes an organic solvent represented by formula (L) (in the formula, L represents a substituent to the benzene ring, and each of a plurality of Ls represents a C1 to C4 alkyl group; and k represents the number of Ls and is an integer of 0 to 5) in an amount of 80 mass % or more.

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According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the islands being formed by the top layer of the active material portion of the one or more tiles.

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

A method includes bonding a first wafer to a second wafer, and performing a trimming process on the first wafer. An edge portion of the first wafer is removed. After the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer. A protection layer is deposited and contacting a sidewall of the first wafer, which deposition process includes depositing a non-oxygen-containing material in contact with the first sidewall. The method further includes removing a horizontal portion of the protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

There is provided a processing method of a workpiece including a necessary region and an unnecessary region. The processing method includes a protective wall forming step of irradiating a region that defines the boundary between the necessary region and the unnecessary region with a laser beam with a wavelength that has transmissibility with respect to the workpiece and forming a plurality of shield tunnels composed of a fine pore and a modified tube that surrounds the fine pore, thereby forming a protective wall, and an unnecessary region removal step of removing the unnecessary region after executing the protective wall forming step.

A method includes forming a first bond layer on a first wafer, and forming a first thermal conductive channel extending into the first bond layer. The first thermal conductive channel has a first thermal conductivity value higher than a second thermal conductivity value of the first bond layer. The method further includes forming a second bond layer on a second wafer, and forming a second thermal conductive channel extending into the second bond layer. The second thermal conductive channel has a third thermal conductivity value higher than a fourth thermal conductivity value of the second bond layer. The first wafer is bonded to the second wafer, and the first thermal conductive channel at least physically contacts the second thermal conductive channel. An interconnect structure is formed over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor layer, a first power bus layer located above the first transistor layer, a second power bus layer located under the second transistor layer, and a first interconnect layer located above the first power bus layer.

A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 μm; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Disclosed are semiconductor packages and methods of fabricating the same. The method inluces forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.