A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A method for manufacturing a handling device includes depositing a single layer of an adhesive on a first surface of a first wafer; depositing an antiadhesive layer on a first surface of a second wafer different from the first wafer; bringing into contact the first wafer and the second wafer, the bringing into contact taking place at the level of the single adhesive layer of the first wafer and the antiadhesive layer of the second wafer; separating the first wafer and the second wafer; the first wafer including the single adhesive layer forming a handling device. The bringing into contact of the first wafer and the second wafer is carried out at a temperature T.sup.C such that T.sub.C>T.sub.g°100°C. where T.sub.g is the glass transition temperature of the material composing the single adhesive layer of the first wafer.

A wafer laminate has an adhesive layer (2) sandwiched between a support (1) and a wafer (3), with a circuit-forming surface of the wafer facing the adhesive layer. The adhesive layer (2) includes a light-shielding resin layer (2a), an epoxy-containing siloxane skeleton resin layer (2b), and a non-silicone thermoplastic resin layer (2c).

A method of manufacturing a semiconductor device includes: forming grooves in a front side surface of a wafer; filling the grooves with a first side face protection material; thinning the wafer at a backside surface of the wafer opposite the front side surface; depositing a backside metallization layer over the backside surface of the thinned wafer; and laser cutting along the grooves through the side face protection material and through the backside metallization layer to separate the wafer into multiple semiconductor devices.

A process of forming an electronic device including providing a substrate having a first surface and a second surface opposite the first surface; etching the substrate along the first surface to define a trench; forming a via within the trench; applying a tape including an adhesive to the first surface, wherein the adhesive of the tape is spaced apart from the first surface by a distance; and operating on the second surface of the substrate.

A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

To protect a plurality of semiconductor chips of a sawn wafer housed in a shipping case and a method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case; the shipping case has the following structure: the shipping case has a lid portion that covers the upper surface of the sawn wafer and a body portion that covers the lower surface of the sawn wafer, the lid portion has a recess portion that covers a plurality of semiconductor chips and a ventilation route communicated with the recess portion. In a step of reducing pressure in the shipping case, a gas in the shipping case is discharged outside via a ventilation route.

A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.