An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.

Disclosed are semiconductor packages and methods of fabricating the same. The method includes forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

A protective member forming apparatus includes an integrating unit that integrates a resin sheet held by a chuck table with a wafer by a resin, a conveying unit that conveys the wafer, and a cutting unit that holds, by a cutting table, the wafer integrated with the resin sheet conveyed by the conveying unit and cuts the resin sheet by a cutting section along the wafer. The cutting unit includes a detection unit that images the wafer by a camera and detects a position of a periphery of the wafer, and a control unit that causes cutting of the resin sheet by the cutting section to be performed only in the case where a peripheral edge of the wafer detected coincides with a track of a cutter blade of the cutting section when the preset resin sheet is cut.

A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.

A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film.

A wafer/support arrangement, including a wafer, a support system, which includes a support and an elastomer layer, and a connecting layer, wherein the connecting layer is a sol-gel layer. The invention further relates to a coated wafer for a wafer/support arrangement according to the invention, wherein a sol-gel layer is used as a connecting layer for a corresponding wafer/support assembly, and to a method for processing the back side of a wafer.

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

A method of dicing an integrated circuit wafer by partially sawing the scribe street from the backside of the wafer and then completing sawing the scribe street from the front side of the wafer. A method of dicing an integrated circuit wafer by backgrinding the wafer prior to partially sawing the scribe street from the backside of the wafer and then completing sawing the scribe street from the front side of the wafer.

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.