A temporary adhesive material for substrate processing adhesion to support the substrate opposite to a surface, the material including: a first temporary adhesive layer; and a second temporary adhesive layer distinct from the first layer, where at least one of the first layer and the second layer has a minimum viscosity of 1 Pa.Math.s or higher and 10,000 Pa.Math.s or lower within 130° C. to 250° C., where: the temporary adhesive material contains 10 parts by mass or more and 100 parts by mass or less of a siloxane bond-containing polymer having a weight-average of 3,000 or more and 700,000 or less as measured by GPC based on a total mass of 100 parts. A temporary material for substrate processing that facilitates the adhesion and separation, allows a quick layer formation, has dimensional resistance to thermal processes, and can raise the productivity of substrates; and manufacturing a laminate using the same.

Provided is a pressure-sensitive adhesive sheet capable of allowing a small electronic part (e.g., a chip having a size of 50 μm/□ or less) to be temporarily fixed in a satisfactory manner and satisfactorily peeled. The pressure-sensitive adhesive sheet of the present invention includes a gas-generating layer configured to generate a gas by being irradiated with laser light, wherein a modulus of elasticity Er(gas) [unit: MPa] of the gas-generating layer measured by a nanoindentation method and a thickness h(gas) [unit: μm] thereof satisfy the following expression (1):

Log(Er(gas)×10.sup.6)≥8.01×h(gas).sup.−0.116  (1).

In one embodiment, the pressure-sensitive adhesive sheet has a transmittance of from 0% to 35% for light having a wavelength of 360 nm. In one embodiment, the pressure-sensitive adhesive sheet has a transmittance of from 10% to 100% for light having a wavelength of 380 nm.

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

This curable resin film forms a first protective film on a surface having bumps of a semiconductor wafer by being attached to the surface and being cured, in which a cured material of the curable resin film has a Young's modulus of equal to or greater than 0.02 MPa and a peak value of a load measured by a probe tack test at 80° C. is equal to or less than 500 g. A first protective film forming sheet is provided with a first supporting sheet, and the curable resin film is provided on one surface of the first supporting sheet.

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

The present invention provides a method for an improved protective coating for plasma dicing a substrate. A work piece having a support film, a frame and the substrate, the substrate having a top surface and a bottom surface, the top surface of the substrate having a plurality of device structures and a plurality of street areas is provided. The work piece is formed by adhering the substrate to a support film and then mounting the substrate with the support film to a frame. A composite material coating having a matrix component and a filler component is applied to the top surface of the substrate. The filler component has a plurality of particles. The composite material coating is removed from at least one street area to expose the street area. The exposed street area is plasma etched. The composite material coating is removed from the top surface of the substrate.

A package structure includes a semiconductor die, a plurality of conductive features, a bridge structure, an underfill, via structures and an encapsulant. The conductive features are electrically connected to the semiconductor die, wherein the conductive features include a first group with planar top surfaces, and a second group with uneven top surfaces. The bridge structure is partially overlapped with the semiconductor die and electrically connected to the first group of the conductive feature. The underfill is covering and contacting the first group of the conductive features. The via structures are disposed on and overlapped with the semiconductor die and electrically connected to the second group of the conductive features. The encapsulant is covering and contacting the via structures and the second group of the conductive features.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.