A method of processing a plate-shaped workpiece includes a workpiece supporting step of placing a plate-shaped workpiece on an upper surface of a sheet whose area is larger than that of the plate-shaped workpiece through a liquid resin interposed therebetween and supporting the plate-shaped workpiece on only the liquid resin that has solidified and the sheet, a processing step of processing the plate-shaped workpiece to divide the plate-shaped workpiece into a plurality of chips, and a pick-up step of picking up the chips from the sheet.

A temporary substrate adhesive according to an embodiment includes a silane coupling agent and a photobase generator, but does not include a resin.

A wafer dividing method of dividing a wafer along each of a plurality of projected dicing lines set in a grid pattern on a front surface of the wafer includes forming a division initiating point serving as an initiating point of division of the wafer along each of the dicing lines, adhering a protective film made of an olefin-based resin and having one surface with no adhesive used therein to the wafer in such a manner that the one surface is brought into intimate contact with the front surface of the wafer, supporting the wafer by a support table in such a manner that the front surface of the wafer and the support table face each other, and applying an external force to the wafer from a back surface side of the wafer to thereby divide the wafer at the division initiating points.

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m.Math.K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

The present invention provides: a temporary adhesive for wafer processing, said temporary adhesive being used for the purpose of provisionally bonding a wafer to a support, while being composed of a photocurable silicone resin composition that contains a non-functional organopolysiloxane; a wafer processed body; and a method for producing a thin wafer, said method using a temporary adhesive for wafer processing.

A method of manufacturing a semiconductor device may include bonding a carrier substrate onto a device wafer using an adhesive member, wherein the adhesive member includes a base film, a device adhesive film disposed on a lower surface of the base film and contacting the device wafer, and a carrier adhesive film disposed on an upper surface of the base film and contacting the carrier substrate. The device adhesive film includes a gas blowing agent, and the carrier adhesive film may not include a gas blowing agent.

A method includes preparing a protective film including a base film and a protective layer laminated on a surface of the base film, mounting the protective film on a semiconductor wafer having a rear surface attached to a dicing tape and a front surface positioned opposite to the rear surface, the protective layer being disposed on the front surface, irradiating the rear surface of the semiconductor wafer with a dicing laser, removing the base film of the protective film from the semiconductor wafer, dividing the semiconductor wafer into individual semiconductor chips, and removing the protective layer from the individual semiconductor chips.