An apparatus for transferring an electronic component is configured to transfer an electronic component on a flexible carrier to a target substrate. The apparatus includes a first frame, a second frame, an abutment module, an actuator, and a negative pressure generating device. The abutment module includes an abutting component and a guide. The guide guides a movement of the abutting component. The actuator actuates the abutment module so that the abutting component and the guide are respectively moved between a start position and an end position of an abutment path. The negative pressure generating device is pumped through the abutment module. When the abutment module abuts against the flexible carrier, a negative pressure is generated between the abutment module and the flexible carrier by the negative pressure generating device. The abutting component and the guide are moved simultaneously in at least a portion of the abutment path.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

An example of a method of making a printed structure comprises providing a destination substrate, contact pads disposed on the destination substrate, and a layer of adhesive disposed on the destination substrate. A stamp with a component adhered to the stamp is provided. The component comprises a stamp side in contact with the stamp and a post side opposite the stamp side, a circuit, and connection posts extending from the post side. Each of the connection posts is electrically connected to the circuit. The component is pressed into contact with the adhesive layer to adhere the component to the destination substrate and to form a printed structure having a volume defined between the component and the destination substrate. The stamp is removed and the printed structure is processed to fill or reduce the volume.

A light-emitting diode substrate, a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the light-emitting diode substrate includes: forming an epitaxial layer group of M light-emitting diode chips on a substrate; transferring N epitaxial layer groups on N substrates onto a transition carrier substrate, the N epitaxial layer groups on the N substrates being densely arranged on the transition carrier substrate; and transferring at least part of N*M light-emitting diode chips corresponding to the N epitaxial layer groups on the transition carrier substrate onto a driving substrate, an area of the transition carrier substrate is greater than or equal to a sum of areas of the N substrates, M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 2.

A micro-device structure includes a substrate having a substrate surface and a substrate contact disposed on or in the substrate surface, a cavity extending into the substrate from the substrate surface, a micro-device disposed in the cavity, the micro-device comprising a micro-device contact, a planarization layer disposed over at least a portion of the substrate, and an electrode disposed at least partially over or on the planarization layer and electrically connected to the micro-device contact.

An embodiment of the present invention provides a transfer film that may be used for both a picking process and a placing process of an element, a transfer method using the transfer film, and an electronic product manufactured using the same. Here, the transfer film according to an embodiment of the present invention includes a base part, an adhesion part, and a first protrusion part. The adhesion part is provided on one surface of the base part, and at least part of the first protrusion part is formed and protruded on one surface of the base part to be accommodated inside the adhesion part, and the thickness increases toward the first direction parallel to the surface of the base part. The first protrusion part is partitioned into a first region including a relatively thick portion of the first protrusion part and a second region including a relatively thin first protrusion part and having weaker adhesive force than the first region, and the element is picked while the first region is lifted first in the picking process, while the element is placed while the second region is lifted first in the placing process.

Provided a semiconductor chip bonding apparatus including a body, a heater disposed on a lower surface of the body, a collet disposed on a lower surface of the heater, and a head disposed on a lower surface of the collet, the head has a rectangular plate shape, a lower surface and side surfaces of the head are exposed, an upper surface of the head is in contact with the lower surface of the collet, an area of the upper surface of the head is smaller than an area of the lower surface of the collet, the head includes a central section including a recess, and an outer surface constituting a part of the side surfaces of the head, and a peripheral section connected to the recess and disposed on each corners of the head, and a thermal conductivity of the peripheral section is different from that of the central section.

In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The microdevices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.